[RTG] Don't hardcode the root op of passes where not necessary (#8791)

include/circt/Dialect/RTG/Transforms/RTGPasses.td

@@ -84,7 +84,7 @@ def InlineSequencesPass : Pass<"rtg-inline-sequences", "mlir::ModuleOp"> {
 }
 
 def LinearScanRegisterAllocationPass : Pass<
-    "rtg-linear-scan-register-allocation", "rtg::TestOp"> {
+    "rtg-linear-scan-register-allocation"> {
 
   let summary = "simple linear scan register allocation for RTG";
   let description = [{
@@ -100,7 +100,7 @@ def LinearScanRegisterAllocationPass : Pass<
   ];
 }
 
-def LowerUniqueLabelsPass : Pass<"rtg-lower-unique-labels", "mlir::ModuleOp"> {
+def LowerUniqueLabelsPass : Pass<"rtg-lower-unique-labels"> {
   let summary = "lower label_unique_decl to label_decl operations";
   let description = [{
     This pass lowers label_unique_decl operations to label_decl operations by
@@ -114,7 +114,7 @@ def LowerUniqueLabelsPass : Pass<"rtg-lower-unique-labels", "mlir::ModuleOp"> {
   ];
 }
 
-def UniqueValidateOpsPass : Pass<"rtg-unique-validate", "mlir::ModuleOp"> {
+def UniqueValidateOpsPass : Pass<"rtg-unique-validate"> {
   let summary = "compute unique IDs for validate operations";
   let description = [{
     This pass visits all 'rtg.validate' operations without an ID attribute and

lib/Dialect/RTG/Transforms/LinearScanRegisterAllocationPass.cpp

@@ -62,14 +62,21 @@ static void expireOldInterval(SmallVector<RegisterLiveRange *> &active,
 }
 
 void LinearScanRegisterAllocationPass::runOnOperation() {
-  auto testOp = getOperation();
-
-  LLVM_DEBUG(llvm::dbgs() << "=== Processing test @" << testOp.getSymName()
+  LLVM_DEBUG(llvm::dbgs() << "=== Processing "
+                          << OpWithFlags(getOperation(),
+                                         OpPrintingFlags().skipRegions())
                           << "\n\n");
 
+  if (getOperation()->getNumRegions() != 1 ||
+      getOperation()->getRegion(0).getBlocks().size() != 1) {
+    getOperation()->emitError("expected a single region with a single block");
+    return signalPassFailure();
+  }
+
   DenseMap<Operation *, unsigned> opIndices;
   unsigned maxIdx;
-  for (auto [i, op] : llvm::enumerate(*testOp.getBody())) {
+  for (auto [i, op] :
+       llvm::enumerate(getOperation()->getRegion(0).getBlocks().front())) {
     // TODO: ideally check that the IR is already fully elaborated
     opIndices[&op] = i;
     maxIdx = i;
@@ -78,7 +85,7 @@ void LinearScanRegisterAllocationPass::runOnOperation() {
   // Collect all the register intervals we have to consider.
   SmallVector<std::unique_ptr<RegisterLiveRange>> regRanges;
   SmallVector<RegisterLiveRange *> active;
-  for (auto &op : *testOp.getBody()) {
+  for (auto &op : getOperation()->getRegion(0).getBlocks().front()) {
     if (!isa<rtg::FixedRegisterOp, rtg::VirtualRegisterOp>(&op))
       continue;
 

lib/Dialect/RTG/Transforms/LowerUniqueLabelsPass.cpp

@@ -42,11 +42,10 @@ struct LowerUniqueLabelsPass
 } // namespace
 
 void LowerUniqueLabelsPass::runOnOperation() {
-  auto moduleOp = getOperation();
   Namespace labelNames;
 
   // Collect all the label names in a first iteration.
-  moduleOp.walk([&](Operation *op) {
+  getOperation()->walk([&](Operation *op) {
     if (auto labelDecl = dyn_cast<LabelDeclOp>(op))
       labelNames.add(labelDecl.getFormatString());
     else if (auto labelDecl = dyn_cast<LabelUniqueDeclOp>(op))
@@ -54,7 +53,7 @@ void LowerUniqueLabelsPass::runOnOperation() {
   });
 
   // Lower the unique labels in a second iteration.
-  moduleOp.walk([&](LabelUniqueDeclOp op) {
+  getOperation()->walk([&](LabelUniqueDeclOp op) {
     // Convert 'rtg.label_unique_decl' to 'rtg.label_decl' by choosing a unique
     // name based on the set of names we collected during elaboration.
     IRRewriter rewriter(op);

lib/Dialect/RTG/Transforms/UniqueValidateOpsPass.cpp

@@ -35,12 +35,11 @@ struct UniqueValidateOpsPass
 } // namespace
 
 void UniqueValidateOpsPass::runOnOperation() {
-  auto moduleOp = getOperation();
   Namespace names;
   SmallVector<ValidateOp> validateOps;
 
   // Collect all the already fixed names in a first iteration.
-  moduleOp.walk([&](ValidateOp op) {
+  getOperation()->walk([&](ValidateOp op) {
     if (op.getId().has_value())
       names.add(op.getId().value());
     else

test/Dialect/RTG/Transform/linear-scan-register-allocation.mlir

@@ -1,4 +1,4 @@
-// RUN: circt-opt --rtg-linear-scan-register-allocation --split-input-file --verify-diagnostics %s | FileCheck %s
+// RUN: circt-opt --pass-pipeline="builtin.module(rtg.test(rtg-linear-scan-register-allocation))" --split-input-file --verify-diagnostics %s | FileCheck %s
 
 // CHECK-LABEL: @test0
 rtg.test @test0() {