mirror of https://github.com/llvm/circt.git
[circt-synth] Add an option to disable WordsToBits, remove verification code from design (#8733)
This modifies circt-synth to make it more practical. * Remove verification code from synthesis parts. ExtarctTestCode is currently used, but eventually it must be replaced with something cleaner. * Add an option to disable wordsToBits.
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@ -38,6 +38,10 @@ struct AIGOptimizationPipelineOptions
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*this, "ignore-abc-failures",
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llvm::cl::desc("Continue on ABC failure instead of aborting"),
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llvm::cl::init(false)};
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PassOptions::Option<bool> disableWordToBits{
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*this, "disable-word-to-bits",
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llvm::cl::desc("Disable LowerWordToBits pass"), llvm::cl::init(false)};
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};
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//===----------------------------------------------------------------------===//
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@ -62,10 +62,11 @@ void circt::synthesis::buildAIGOptimizationPipeline(
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pm.addPass(aig::createLowerVariadic());
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// TODO: LowerWordToBits is not scalable for large designs. Change to
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// conditionally enable the pass once the rest of the pipeline was able
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// to handle multibit operands properly.
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pm.addPass(aig::createLowerWordToBits());
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// LowerWordToBits may not be scalable for large designs so conditionally
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// disable it. It's also worth considering keeping word-level representation
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// for faster synthesis.
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if (!options.disableWordToBits)
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pm.addPass(aig::createLowerWordToBits());
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pm.addPass(createCSEPass());
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pm.addPass(createSimpleCanonicalizerPass());
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@ -3,12 +3,14 @@
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// RUN: circt-synth %s --top and --emit-bytecode -f | circt-opt | FileCheck %s --check-prefix=CHECK
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// RUN: circt-synth %s --until-before aig-lowering | FileCheck %s --check-prefix=AIG
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// RUN: circt-synth %s --until-before aig-lowering --convert-to-comb | FileCheck %s --check-prefix=COMB
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// RUN: circt-synth %s --top and --disable-word-to-bits | FileCheck %s --check-prefix=DISABLE_WORD
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// TOP-LABEL: module attributes {"aig.longest-path-analysis-top" = @and}
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// AIG-LABEL: @and
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// CHECK-LABEL: @and
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// COMB-LABEL: @and
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hw.module @and(in %a: i2, in %b: i2, in %c: i2, out and: i2) {
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// AIG-LABEL: @and(
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// CHECK-LABEL: @and(
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// COMB-LABEL: @and(
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// DISABLE_WORD-LABEL: @and(
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hw.module @and(in %a: i2, in %b: i2, in %c: i2, in %d: i1, out and: i2) {
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// AIG-NEXT: %[[AND_INV:.+]] = aig.and_inv %a, %b, %c : i2
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// AIG-NEXT: dbg.variable
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// AIG-NEXT: hw.output %[[AND_INV]] : i2
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@ -26,11 +28,22 @@ hw.module @and(in %a: i2, in %b: i2, in %c: i2, out and: i2) {
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// CHECK-NEXT: dbg.variable
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// CHECK-NEXT: hw.output %[[CONCAT]] : i2
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// COMB-NOT: aig.and_inv
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// DISABLE_WORD-NOT: comb.extract
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// DISABLE_WORD-NOT: comb.concat
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%0 = comb.and %a, %b, %c : i2
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dbg.variable "test", %0 : i2
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hw.output %0 : i2
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}
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// CHECK-LABEL: @verification(
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// CHECK-NOT: sv.assert
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hw.module @verification(in %a: i1, out result: i1) {
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sv.initial {
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sv.assert %a, immediate
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}
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hw.output %a : i1
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}
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// TOP-LABEL: hw.module @unrelated
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// TOP-NEXT: comb.add %a, %b
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hw.module @unrelated(in %a: i2, in %b: i2, out and: i2) {
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@ -13,6 +13,7 @@ target_link_libraries(circt-synth
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CIRCTSeq
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CIRCTSim
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CIRCTSV
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CIRCTSVTransforms
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CIRCTSynthesis
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CIRCTTransforms
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CIRCTVerif
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@ -24,6 +24,7 @@
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#include "circt/Dialect/LTL/LTLDialect.h"
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#include "circt/Dialect/OM/OMDialect.h"
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#include "circt/Dialect/SV/SVDialect.h"
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#include "circt/Dialect/SV/SVPasses.h"
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#include "circt/Dialect/Seq/SeqDialect.h"
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#include "circt/Dialect/Sim/SimDialect.h"
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#include "circt/Dialect/Verif/VerifDialect.h"
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@ -144,6 +145,10 @@ static cl::opt<bool>
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cl::desc("Continue on ABC failure instead of aborting"),
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cl::init(false), cl::cat(mainCategory));
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static cl::opt<bool> disableWordToBits("disable-word-to-bits",
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cl::desc("Disable LowerWordToBits pass"),
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cl::init(false), cl::cat(mainCategory));
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//===----------------------------------------------------------------------===//
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// Main Tool Logic
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//===----------------------------------------------------------------------===//
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@ -174,6 +179,11 @@ static void partiallyLegalizeCombToAIG(SmallVectorImpl<std::string> &ops) {
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// Add a default synthesis pipeline and analysis.
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static void populateCIRCTSynthPipeline(PassManager &pm) {
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// ExtractTestCode is used to move verification code from design to
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// remove registers/logic used only for verification.
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pm.addPass(sv::createSVExtractTestCodePass(
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/*disableInstanceExtraction=*/false, /*disableRegisterExtraction=*/false,
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/*disableModuleInlining=*/false));
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auto pipeline = [](OpPassManager &pm) {
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circt::synthesis::buildAIGLoweringPipeline(pm);
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if (untilReached(UntilAIGLowering))
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@ -183,6 +193,7 @@ static void populateCIRCTSynthPipeline(PassManager &pm) {
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options.abcCommands = abcCommands;
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options.abcPath.setValue(abcPath);
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options.ignoreAbcFailures.setValue(ignoreAbcFailures);
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options.disableWordToBits.setValue(disableWordToBits);
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circt::synthesis::buildAIGOptimizationPipeline(pm, options);
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};
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