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[ImportVerilog] Ignore forward typedefs 

Ignore `ForwardingTypedefSymbol` AST nodes, since Slang already deals
with these when it does type checking. We don't need them to show up in
the final IR.
This commit is contained in:
Fabian Schuiki 2025-04-16 11:18:03 -07:00
parent c190ff421b
commit bd5553bc78
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2 changed files with 24 additions and 1 deletions
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3
lib/Conversion/ImportVerilog/Structure.cpp
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@ -55,6 +55,9 @@ struct BaseVisitor {
// Skip typedefs.
LogicalResult visit(const slang::ast::TypeAliasType &) { return success(); }
LogicalResult visit(const slang::ast::ForwardingTypedefSymbol &) {
return success();
}
// Skip imports. The AST already has its names resolved.
LogicalResult visit(const slang::ast::ExplicitImportSymbol &) {

22
test/Conversion/ImportVerilog/basic.sv
View File

@ -11,10 +11,30 @@ timeprecision 10fs;
timeunit 100ps/10fs;
`timescale 100ps/10fs;
// Ignore type aliases and enum variant names imported into the parent scope.
// Ignore type aliases, forward declarations of type aliases, and enum variant
// names imported into the parent scope. These are resolved by Slang.
typedef MyInt;
typedef int MyInt;
typedef MyInt;
typedef MyInt;
typedef enum { VariantA, VariantB } MyEnum;
module Typedefs1;
typedef MyInt2;
typedef int MyInt2;
typedef MyInt2;
typedef MyInt2;
typedef enum { VariantC, VariantD } MyEnum2;
endmodule
function void Typedefs2();
typedef MyInt2;
typedef int MyInt2;
typedef MyInt2;
typedef MyInt2;
typedef enum { VariantC, VariantD } MyEnum2;
endfunction
// Ignore imports.
import Package::*;