Bump LLVM to dd115e5a9bc7

This bumps llvm.  There is an upstream bug which affects DC.join.  Some folders and tests are disabled due to this.

---------

Co-authored-by: Andrew Young <youngar17@gmail.com>
Co-authored-by: Andrew Lenharth <andrew@lenharth.org>

include/circt/Dialect/Arc/ArcInterfaces.td

@@ -12,22 +12,6 @@
 include "mlir/IR/OpBase.td"
 include "mlir/Interfaces/CallInterfaces.td"
 
-def CallOpMutableInterface : OpInterface<"CallOpMutableInterface", [CallOpInterface]> {
-  let description = [{
-    Can be implemented in addition to `CallOpInterface` to allow mutation of the
-    call operation.
-  }];
-  let cppNamespace = "::circt::arc";
-
-  let methods = [
-    InterfaceMethod<[{
-        Returns the operands within this call that are used as arguments to the
-        callee as a mutable range.
-      }],
-      "::mlir::MutableOperandRange", "getArgOperandsMutable">,
-  ];
-}
-
 def ClockedOpInterface : OpInterface<"ClockedOpInterface"> {
   let description = [{
     This interface should be implemented by operations that have clocked

include/circt/Dialect/Arc/ArcOps.td

@@ -132,7 +132,7 @@ def OutputOp : ArcOp<"output", [
 
 def StateOp : ArcOp<"state", [
   MemRefsNormalizable,
-  CallOpMutableInterface,
+  CallOpInterface,
   DeclareOpInterfaceMethods<SymbolUserOpInterface>,
   AttrSizedOperandSegments,
   DeclareOpInterfaceMethods<ClockedOpInterface, ["isClocked"]>,
@@ -232,7 +232,7 @@ def StateOp : ArcOp<"state", [
 
 def CallOp : ArcOp<"call", [
   MemRefsNormalizable, Pure,
-  CallOpMutableInterface,
+  CallOpInterface,
   DeclareOpInterfaceMethods<SymbolUserOpInterface>
 ]> {
   let summary = "calls an arc";
@@ -312,7 +312,7 @@ def MemoryReadPortOp : ArcOp<"memory_read_port", [
 
 def MemoryWritePortOp : ArcOp<"memory_write_port", [
   MemoryEffects<[MemWrite]>,
-  CallOpMutableInterface,
+  CallOpInterface,
   DeclareOpInterfaceMethods<SymbolUserOpInterface>,
   AttrSizedOperandSegments,
   ClockedOpInterface

include/circt/Dialect/Handshake/HandshakeOps.td

@@ -183,6 +183,11 @@ def InstanceOp : Handshake_Op<"instance", [
     Value getControl() {
       return getOperands().back();
     }
+
+    MutableOperandRange getArgOperandsMutable() {
+      return getOpOperandsMutable();
+    }
+
   }];
 
   let assemblyFormat = [{

include/circt/Dialect/Ibis/IbisOps.td

@@ -136,6 +136,10 @@ def CallOp : IbisOp<"call", [CallOpInterface]> {
   let results = (outs Variadic<AnyType>);
 
   let extraClassDeclaration = [{
+    MutableOperandRange getArgOperandsMutable() {
+      return getOperandsMutable();
+    }
+
     /// Get the argument operands to the called method.
     operand_range getArgOperands() {
       return {arg_operand_begin(), arg_operand_end()};

include/circt/Dialect/LLHD/IR/StructureOps.td

@@ -197,6 +197,10 @@ def LLHD_InstOp : LLHD_Op<"inst", [
   let extraClassDeclaration = [{
     FunctionType getCalleeType();
 
+    MutableOperandRange getArgOperandsMutable() {
+      return getInputsMutable();
+    }
+
     /// Get the argument operands to the called function.
     operand_range getArgOperands() {
       return {arg_operand_begin(), arg_operand_end()};

include/circt/Dialect/SystemC/SystemCStatements.td

@@ -257,6 +257,10 @@ def CallIndirectOp : SystemCOp<"cpp.call_indirect", [
     }]>];
 
   let extraClassDeclaration = [{
+    MutableOperandRange getArgOperandsMutable() {
+      return getCalleeOperandsMutable();
+    }
+
     /// Get the argument operands to the called function.
     operand_range getArgOperands() {
       return {arg_operand_begin(), arg_operand_end()};
@@ -329,6 +333,10 @@ def CallOp : SystemCOp<"cpp.call", [
 
   let extraClassDeclaration = [{
     FunctionType getCalleeType();
+    
+    MutableOperandRange getArgOperandsMutable() {
+      return getCalleeOperandsMutable();
+    }
 
     /// Get the argument operands to the called function.
     operand_range getArgOperands() {

lib/Dialect/Arc/ArcOps.cpp

@@ -285,11 +285,6 @@ LogicalResult LutOp::verify() {
   return success();
 }
 
-Operation *
-CallOpMutableInterface::resolveCallable(SymbolTableCollection *symbolTable) {
-  return cast<CallOpInterface>(**this).resolveCallable(symbolTable);
-}
-
 #include "circt/Dialect/Arc/ArcInterfaces.cpp.inc"
 
 #define GET_OP_CLASSES

lib/Dialect/Arc/Transforms/ArcCanonicalizer.cpp

@@ -389,9 +389,9 @@ LogicalResult RemoveUnusedArcArgumentsPattern::matchAndRewrite(
   // Collect the mutable callers in a first iteration. If there is a user that
   // does not implement the interface, we have to abort the rewrite and have to
   // make sure that we didn't change anything so far.
-  SmallVector<CallOpMutableInterface> mutableUsers;
+  SmallVector<mlir::CallOpInterface> mutableUsers;
   for (auto *user : symbolCache.getUsers(op)) {
-    auto callOpMutable = dyn_cast<CallOpMutableInterface>(user);
+    auto callOpMutable = dyn_cast<mlir::CallOpInterface>(user);
     if (!callOpMutable)
       return failure();
     mutableUsers.push_back(callOpMutable);
@@ -418,14 +418,14 @@ SinkArcInputsPattern::matchAndRewrite(DefineOp op,
   // modify the users.
   auto users = symbolCache.getUsers(op);
   if (llvm::any_of(
-          users, [](auto *user) { return !isa<CallOpMutableInterface>(user); }))
+          users, [](auto *user) { return !isa<mlir::CallOpInterface>(user); }))
     return failure();
 
   // Find all arguments that use constant operands only.
   SmallVector<Operation *> stateConsts(op.getNumArguments());
   bool first = true;
   for (auto *user : users) {
-    auto callOp = cast<CallOpMutableInterface>(user);
+    auto callOp = cast<mlir::CallOpInterface>(user);
     for (auto [constArg, input] :
          llvm::zip(stateConsts, callOp.getArgOperands())) {
       if (auto *constOp = input.getDefiningOp();
@@ -461,7 +461,7 @@ SinkArcInputsPattern::matchAndRewrite(DefineOp op,
 
   // Rewrite all arc uses to not pass in the constant anymore.
   for (auto *user : users) {
-    auto callOp = cast<CallOpMutableInterface>(user);
+    auto callOp = cast<mlir::CallOpInterface>(user);
     SmallPtrSet<Value, 4> maybeUnusedValues;
     SmallVector<Value> newInputs;
     for (auto [index, value] : llvm::enumerate(callOp.getArgOperands())) {

lib/Dialect/Arc/Transforms/Dedup.cpp

@@ -321,7 +321,7 @@ private:
 } // namespace
 
 static void addCallSiteOperands(
-    MutableArrayRef<CallOpMutableInterface> callSites,
+    MutableArrayRef<mlir::CallOpInterface> callSites,
     ArrayRef<std::variant<Operation *, unsigned>> operandMappings) {
   SmallDenseMap<Operation *, Operation *> clonedOps;
   SmallVector<Value> newOperands;
@@ -358,7 +358,7 @@ struct DedupPass : public DedupBase<DedupPass> {
   /// A mapping from arc names to arc definitions.
   DenseMap<StringAttr, DefineOp> arcByName;
   /// A mapping from arc definitions to call sites.
-  DenseMap<DefineOp, SmallVector<CallOpMutableInterface, 1>> callSites;
+  DenseMap<DefineOp, SmallVector<mlir::CallOpInterface, 1>> callSites;
 };
 
 struct ArcHash {
@@ -384,7 +384,7 @@ void DedupPass::runOnOperation() {
   }
 
   // Collect the arc call sites.
-  getOperation().walk([&](CallOpMutableInterface callOp) {
+  getOperation().walk([&](mlir::CallOpInterface callOp) {
     if (auto defOp =
             dyn_cast_or_null<DefineOp>(callOp.resolveCallable(&symbolTable)))
       callSites[arcByName.lookup(callOp.getCallableForCallee()

lib/Dialect/DC/DCOps.cpp

@@ -38,6 +38,10 @@ OpFoldResult JoinOp::fold(FoldAdaptor adaptor) {
   if (auto tokens = getTokens(); tokens.size() == 1)
     return tokens.front();
 
+  // These folders are disabled to work around MLIR bugs when changing
+  // the number of operands.  https://github.com/llvm/llvm-project/issues/64280
+  return {};
+
   // Remove operands which originate from a dc.source op (redundant).
   auto *op = getOperation();
   for (OpOperand &operand : llvm::make_early_inc_range(op->getOpOperands())) {

lib/Dialect/FIRRTL/Transforms/IMConstProp.cpp

@@ -839,10 +839,12 @@ void IMConstPropPass::visitOperation(Operation *op, FieldRef changedField) {
     logger.getOStream() << "}\n";
   });
 
-  // Fold functions in general are allowed to do in-place updates, but FIRRTL
+  // If the folding was in-place, keep going.  This is surprising, but since
-  // does not do this and supporting it costs more.
+  // only folder that will do inplace updates is the communative folder, we
-  assert(!foldResults.empty() &&
+  // aren't going to stop.  We don't update the results, since they didn't
-         "FIRRTL fold functions shouldn't do in-place updates!");
+  // change, the op just got shuffled around.
+  if (foldResults.empty())
+    return visitOperation(op, changedField);
 
   // Merge the fold results into the lattice for this operation.
   assert(foldResults.size() == op->getNumResults() && "invalid result size");
@@ -860,11 +862,8 @@ void IMConstPropPass::visitOperation(Operation *op, FieldRef changedField) {
           latticeValues[getOrCacheFieldRefFromValue(foldResult.get<Value>())];
     }
 
-    // We do not "merge" the lattice value in, we set it.  This is because the
+    mergeLatticeValue(getOrCacheFieldRefFromValue(op->getResult(i)),
-    // fold functions can produce different values over time, e.g. in the
+                      resultLattice);
-    // presence of InvalidValue operands that get resolved to other constants.
-    setLatticeValue(getOrCacheFieldRefFromValue(op->getResult(i)),
-                    resultLattice);
   }
 }
 

lib/Dialect/SV/Transforms/HWMemSimImpl.cpp

@@ -640,7 +640,7 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) {
                 // Truncate the induction variable if necessary.
                 if (!outerIndVar.getType().isInteger(
                         llvm::Log2_64_Ceil(mem.depth)))
-                  iterValue = b.create<comb::ExtractOp>(
+                  iterValue = b.createOrFold<comb::ExtractOp>(
                       iterValue, 0, llvm::Log2_64_Ceil(mem.depth));
                 auto lhs = b.create<sv::ArrayIndexInOutOp>(reg, iterValue);
                 auto rhs = b.createOrFold<comb::ExtractOp>(

lib/Dialect/Seq/Transforms/LowerFirMem.cpp

@@ -105,7 +105,7 @@ namespace {
 struct LowerFirMemPass : public impl::LowerFirMemBase<LowerFirMemPass> {
   /// A vector of unique `FirMemConfig`s and all the `FirMemOp`s that use it.
   using UniqueConfig = std::pair<FirMemConfig, SmallVector<FirMemOp, 1>>;
-  using UniqueConfigs = std::vector<UniqueConfig>;
+  using UniqueConfigs = SmallVector<UniqueConfig>;
 
   void runOnOperation() override;
 

llvm

@@ -1 +1 @@
-Subproject commit 0a35ac6c2e0cb0160ca2e6cc11644c263692a46d
+Subproject commit a133fb289af4f3eef018ddf961f1f2ed129d0c2d

test/Analysis/dependence-analysis.mlir

@@ -120,6 +120,9 @@ func.func @test7(%arg0: memref<?xi32>) {
         // CHECK: affine.load %arg0[%arg1] {dependences = []}
         %1 = affine.load %arg0[%arg1] : memref<?xi32>
         affine.yield %1 : i32
+      } else {
+        %1 = arith.constant 0 : i32
+        affine.yield %1 : i32
       }
       // CHECK{LITERAL}: affine.store %0, %arg0[%arg1] {dependences = [[[0, 0]]]}
       affine.store %0, %arg0[%arg1] : memref<?xi32>

test/Analysis/scheduling-analysis.mlir

@@ -109,6 +109,9 @@ func.func @test7(%arg0: memref<?xi32>) {
       %0 = affine.if #set3(%arg1) -> i32 {
         %1 = affine.load %arg0[%arg1] : memref<?xi32>
         affine.yield %1 : i32
+      } else {
+        %1 = arith.constant 0 : i32
+        affine.yield %1 : i32
       }
       // CHECK: } {dependence}
       // CHECK: affine.store %0, %arg0[%arg1] {dependence}

test/Conversion/FIRRTLToHW/lower-to-hw.mlir

@@ -83,7 +83,7 @@ firrtl.circuit "Simple"   attributes {annotations = [{class =
     firrtl.connect %out5, %tmp1 : !firrtl.uint<4>, !firrtl.uint<4>
 
     // CHECK: [[ZEXT:%.+]] = comb.concat %false, %in1 : i1, i4
-    // CHECK: [[ADD:%.+]] = comb.add bin %c12_i5, [[ZEXT]] : i5
+    // CHECK: [[ADD:%.+]] = comb.add bin [[ZEXT]], %c12_i5 : i5
     %0 = firrtl.add %c12_ui4, %in1 : (!firrtl.uint<4>, !firrtl.uint<4>) -> !firrtl.uint<5>
 
     %1 = firrtl.asUInt %in1 : (!firrtl.uint<4>) -> !firrtl.uint<4>

test/Conversion/FIRRTLToHW/zero-width.mlir

@@ -25,7 +25,7 @@ firrtl.circuit "Arithmetic" {
     // CHECK-DAG: %c0_i4 = hw.constant 0 : i4
     // CHECK-DAG: %false = hw.constant false
     // CHECK-NEXT: [[UIN3EXT:%.+]] = comb.concat %false, %uin3c : i1, i3
-    // CHECK-NEXT: [[ADDRES:%.+]] = comb.add bin %c0_i4, [[UIN3EXT]] : i4
+    // CHECK-NEXT: [[ADDRES:%.+]] = comb.add bin [[UIN3EXT]], %c0_i4 : i4
     %1 = firrtl.add %uin0c, %uin3c : (!firrtl.uint<0>, !firrtl.uint<3>) -> !firrtl.uint<4>
     firrtl.connect %out1, %1 : !firrtl.uint<4>, !firrtl.uint<4>
 

test/Dialect/DC/canonicalization.mlir

@@ -1,4 +1,6 @@
 // RUN: circt-opt %s --canonicalize --cse --canonicalize | FileCheck %s
+// XFAIL: *
+// Waiting on: https://github.com/llvm/llvm-project/issues/64280
 
 // CHECK-LABEL:   func.func @staggeredJoin1(
 // CHECK-SAME:                    %[[VAL_0:.*]]: !dc.token,

test/Dialect/ESI/lowering.mlir

@@ -67,7 +67,7 @@ hw.module @add11(%clk: i1, %ints: !esi.channel<i32>) -> (mutatedInts: !esi.chann
 }
 // HW-LABEL: hw.module @add11(%clk: i1, %ints: i32, %ints_valid: i1, %mutatedInts_ready: i1) -> (ints_ready: i1, mutatedInts: i32, mutatedInts_valid: i1, c4: i4) {
 // HW:   %{{.+}} = hw.constant 11 : i32
-// HW:   [[RES0:%.+]] = comb.add %{{.+}}, %ints : i32
+// HW:   [[RES0:%.+]] = comb.add %ints, %{{.+}} : i32
 // HW:   %{{.+}} = hw.constant 0 : i4
 // HW:   hw.output %mutatedInts_ready, [[RES0]], %ints_valid, %{{.+}} : i1, i32, i1, i4
 

test/Dialect/SV/hw-memsim.mlir

@@ -97,7 +97,7 @@ hw.module.generated @FIRRTLMem_1_1_1_16_10_0_1_0_0, @FIRRTLMem(%ro_addr_0: i4, %
 //CHECK-NEXT:  %[[rwdata2:.+]] = comb.mux %[[rwrcond]], %[[rwdata]], %[[x2]]
 //CHECK-NEXT:  sv.assign %[[rwtmp]], %[[rwdata2:.+]]
 //CHECK-NEXT:    sv.always posedge %rw_clock_0 {
-//CHECK-NEXT:      %[[rwwcondpre:.+]] = comb.and %true, %rw_wmode_0
+//CHECK-NEXT:      %[[rwwcondpre:.+]] = comb.and %rw_wmode_0, %true
 //CHECK-NEXT:      %[[rwwcond:.+]] = comb.and %rw_en_0, %[[rwwcondpre]]
 //CHECK-NEXT:      sv.if %[[rwwcond]]  {
 //CHECK-NEXT:        %[[rwwslot:.+]] = sv.array_index_inout %Memory[%rw_addr_0]
@@ -370,7 +370,7 @@ hw.module.generated @ReadWriteWithHighReadLatency, @FIRRTLMem(%rw_addr: i4, %rw_
 
 // Write port
 // CHECK: sv.always
-// CHECK: [[TMP:%.+]] = comb.and %true, [[WMODE_1R]]
+// CHECK: [[TMP:%.+]] = comb.and [[WMODE_1R]], %true
 // CHECK: [[WCOND:%.+]] comb.and [[EN_1R]], [[TMP]]
 // CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[ADDR_1R]]]
 
@@ -419,6 +419,6 @@ hw.module.generated @ReadWriteWithHighWriteLatency, @FIRRTLMem(%rw_addr: i4, %rw
 
 // Write port
 // CHECK: sv.always
-// CHECK: [[TMP:%.+]] = comb.and %true, [[WRITE_WMODE_3R]]
+// CHECK: [[TMP:%.+]] = comb.and [[WRITE_WMODE_3R]], %true
 // CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[TMP]]
 // CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[WRITE_ADDR_3R]]]