mirror of https://github.com/llvm/circt.git
Add SitestBlackBoxLibrariesAnnotation; process in CreateSiFiveMetadataPass (#8670)
This commit is contained in:
Trevor McKay
GitHub
parent
713a91ddff
commit
bffff7d9a2
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@ -766,10 +766,14 @@ Example:
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| filename | string | The file to write to |
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This annotation triggers the creation of a file containing a JSON array of the
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names of all external modules in the device under test which are not imported
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`defname`s of all external modules in the device under test which are not imported
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or inlined blackbox modules. This will only collect modules which are
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instantiated under a module annotated with `MarkDUTAnnotation`.
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If any external modules (including imported and inlined blackboxes) have a
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`SitestBlackBoxLibrariesAnnotation`, the libraries specified in that annotation
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will be included in the output.
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Example:
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```json
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{
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@ -786,10 +790,14 @@ Example:
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| filename | string | The file to write to |
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This annotation triggers the creation of a file containing a JSON array of the
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names of all external modules in the test harness which are not imported or
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`defname`s of all external modules in the test harness which are not imported or
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inlined blackbox modules. This will only collect modules which are not
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instantiated under a module annotated with `MarkDUTAnnotation`.
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If any external modules (including imported and inlined blackboxes) have a
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`SitestBlackBoxLibrariesAnnotation`, the libraries specified in that annotation
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will also be included in the output.
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Example:
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```json
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{
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@ -798,6 +806,28 @@ Example:
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}
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```
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### SitestBlackBoxLibrariesAnnotation
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| Property | Type | Description |
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| ---------- | ------ | ------------- |
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| class | string | `sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation` |
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| libraries | array | Array of library names to include in blackbox metadata |
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This annotation is used to specify additional library names that should be
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included in the blackbox metadata for an external module. When applied to an
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external module, the specified libraries will be added to the blackbox resource
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list in the generated metadata. Both the `defname` and any libraries specified by
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this annotation will be included in the metadata for non-imported and non-inlined
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blackboxes.
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Example:
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```json
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{
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"class":"sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation",
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"libraries":["libmath", "libcrypto", "custom_lib"]
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}
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```
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### TestBenchDirAnnotation
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| Property | Type | Description |
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@ -143,6 +143,8 @@ constexpr const char *sitestBlackBoxAnnoClass =
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"sifive.enterprise.firrtl.SitestBlackBoxAnnotation";
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constexpr const char *sitestTestHarnessBlackBoxAnnoClass =
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"sifive.enterprise.firrtl.SitestTestHarnessBlackBoxAnnotation";
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constexpr const char *sitestBlackBoxLibrariesAnnoClass =
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"sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation";
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constexpr const char *dontObfuscateModuleAnnoClass =
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"sifive.enterprise.firrtl.DontObfuscateModuleAnnotation";
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constexpr const char *elaborationArtefactsDirectoryAnnoClass =
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@ -165,7 +165,9 @@ struct ObjectModelIR {
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auto unknownLoc = mlir::UnknownLoc::get(context);
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auto builderOM = mlir::ImplicitLocOpBuilder::atBlockEnd(
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unknownLoc, circtOp.getBodyBlock());
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Type classFieldTypes[] = {StringType::get(context), BoolType::get(context)};
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Type classFieldTypes[] = {
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StringType::get(context), BoolType::get(context),
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ListType::get(context, cast<PropertyType>(StringType::get(context)))};
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blackBoxModulesSchemaClass =
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builderOM.create<ClassOp>("SitestBlackBoxModulesSchema",
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blackBoxModulesParamNames, classFieldTypes);
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@ -174,7 +176,8 @@ struct ObjectModelIR {
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builderOM.getStringAttr("SitestBlackBoxMetadata"), mports);
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}
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void addBlackBoxModule(FExtModuleOp module, bool inDut) {
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void addBlackBoxModule(FExtModuleOp module, bool inDut,
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ArrayRef<StringRef> libraries) {
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if (!blackBoxModulesSchemaClass)
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addBlackBoxModulesSchema();
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StringRef defName = *module.getDefname();
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@ -184,6 +187,24 @@ struct ObjectModelIR {
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module.getLoc(), blackBoxMetadataClass.getBodyBlock());
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auto modEntry = builderOM.create<StringConstantOp>(module.getDefnameAttr());
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auto inDutAttr = builderOM.create<BoolConstantOp>(inDut);
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SmallVector<Value> libValues;
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for (StringRef libName : libraries) {
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Value libNameAttr;
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if (libName == defName) {
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libNameAttr = modEntry;
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} else {
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libNameAttr = builderOM.create<StringConstantOp>(
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builderOM.getStringAttr(libName));
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}
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libValues.push_back(libNameAttr);
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}
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auto blackBoxResourcesList = builderOM.create<ListCreateOp>(
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ListType::get(
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builderOM.getContext(),
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cast<PropertyType>(StringType::get(builderOM.getContext()))),
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libValues);
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auto object = builderOM.create<ObjectOp>(blackBoxModulesSchemaClass,
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module.getModuleNameAttr());
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@ -191,6 +212,10 @@ struct ObjectModelIR {
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builderOM.create<PropAssignOp>(inPortModuleName, modEntry);
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auto inPortInDut = builderOM.create<ObjectSubfieldOp>(object, 2);
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builderOM.create<PropAssignOp>(inPortInDut, inDutAttr);
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auto inPortBlackBoxResources =
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builderOM.create<ObjectSubfieldOp>(object, 4);
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builderOM.create<PropAssignOp>(inPortBlackBoxResources,
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blackBoxResourcesList);
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auto portIndex = blackBoxMetadataClass.getNumPorts();
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SmallVector<std::pair<unsigned, PortInfo>> newPorts = {
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{portIndex,
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@ -463,7 +488,7 @@ struct ObjectModelIR {
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"readLatency", "hierarchy", "inDut", "extraPorts",
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"preExtInstName"};
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StringRef retimeModulesParamNames[1] = {"moduleName"};
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StringRef blackBoxModulesParamNames[2] = {"moduleName", "inDut"};
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StringRef blackBoxModulesParamNames[3] = {"moduleName", "inDut", "libraries"};
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llvm::SmallDenseSet<StringRef> blackboxModules;
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}; // namespace
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@ -797,7 +822,7 @@ LogicalResult
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CreateSiFiveMetadataPass::emitSitestBlackboxMetadata(ObjectModelIR &omir) {
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// Any extmodule with these annotations should be excluded from the blackbox
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// list.
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// list if it doesn't declare any additional libraries.
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std::array<StringRef, 6> blackListedAnnos = {
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blackBoxAnnoClass, blackBoxInlineAnnoClass, blackBoxPathAnnoClass,
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dataTapsBlackboxClass, memTapBlackboxClass};
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@ -819,30 +844,52 @@ CreateSiFiveMetadataPass::emitSitestBlackboxMetadata(ObjectModelIR &omir) {
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// Find all extmodules in the circuit. Check if they are black-listed from
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// being included in the list. If they are not, separate them into two
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// groups depending on if theyre in the DUT or the test harness.
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SmallVector<StringRef> dutModules;
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SmallVector<StringRef> testModules;
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SmallVector<StringRef> dutLibs;
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SmallVector<StringRef> testLibs;
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for (auto extModule : circuitOp.getBodyBlock()->getOps<FExtModuleOp>()) {
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SmallVector<StringRef> libs;
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// If the module doesn't have a defname, then we can't record it properly.
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// Just skip it.
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if (!extModule.getDefname())
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continue;
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// If its a generated blackbox, skip it.
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AnnotationSet annos(extModule);
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if (llvm::any_of(blackListedAnnos, [&](auto blackListedAnno) {
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bool isBlacklistedBlackbox =
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llvm::any_of(blackListedAnnos, [&](auto blackListedAnno) {
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return annos.hasAnnotation(blackListedAnno);
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}))
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});
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if (!isBlacklistedBlackbox)
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libs.push_back(*extModule.getDefname());
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bool hasLibs = false;
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if (auto libsAnno = annos.getAnnotation(sitestBlackBoxLibrariesAnnoClass)) {
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if (auto libsAttr = libsAnno.getMember<ArrayAttr>("libraries")) {
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for (auto lib : libsAttr) {
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if (auto libStr = dyn_cast<StringAttr>(lib)) {
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libs.push_back(libStr.getValue());
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hasLibs = true;
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}
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}
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}
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}
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if (libs.empty())
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continue;
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// Record the defname of the module.
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bool inDut = false;
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if (instanceInfo->anyInstanceInEffectiveDesign(extModule)) {
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inDut = true;
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dutModules.push_back(*extModule.getDefname());
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} else {
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testModules.push_back(*extModule.getDefname());
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}
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omir.addBlackBoxModule(extModule, inDut);
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for (StringRef lib : libs)
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dutLibs.push_back(lib);
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} else
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for (StringRef lib : libs)
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testLibs.push_back(lib);
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omir.addBlackBoxModule(extModule, inDut, libs);
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}
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// This is a helper to create the verbatim output operation.
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@ -874,8 +921,8 @@ CreateSiFiveMetadataPass::emitSitestBlackboxMetadata(ObjectModelIR &omir) {
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});
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};
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createOutput(testModules, testFilename);
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createOutput(dutModules, dutFilename);
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createOutput(testLibs, testFilename);
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createOutput(dutLibs, dutFilename);
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return success();
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}
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@ -630,6 +630,8 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
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{injectDUTHierarchyAnnoClass, NoTargetAnnotation},
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{convertMemToRegOfVecAnnoClass, NoTargetAnnotation},
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{sitestBlackBoxAnnoClass, NoTargetAnnotation},
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{sitestBlackBoxLibrariesAnnoClass,
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{stdResolve, applyWithoutTarget<false, FExtModuleOp>}},
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{enumComponentAnnoClass, {noResolve, drop}},
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{enumDefAnnoClass, {noResolve, drop}},
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{enumVecAnnoClass, {noResolve, drop}},
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@ -135,20 +135,23 @@ circuit TestHarness:
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; SITEST_NODUT: FILE "testbench.sitest.json"
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; SITEST_NODUT-NOT: FILE
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; MLIR_OUT: om.class @SitestBlackBoxModulesSchema(%basepath: !om.basepath, %moduleName_in: !om.string, %inDut_in: i1) -> (moduleName: !om.string, inDut: i1) {
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; MLIR_OUT: om.class.fields %moduleName_in, %inDut_in : !om.string, i1
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; MLIR_OUT: om.class @SitestBlackBoxModulesSchema(%basepath: !om.basepath, %moduleName_in: !om.string, %inDut_in: i1, %libraries_in: !om.list<!om.string>) -> (moduleName: !om.string, inDut: i1, libraries: !om.list<!om.string>) {
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; MLIR_OUT: om.class.fields %moduleName_in, %inDut_in, %libraries_in : !om.string, i1, !om.list<!om.string>
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; MLIR_OUT: }
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; MLIR_OUT: om.class @SitestBlackBoxMetadata(%basepath: !om.basepath) -> [[V1:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V2:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>, [[V3:.+]]: !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[STR1:%.+]] = om.constant "Foo_BlackBox" : !om.string
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; MLIR_OUT-DAG: [[DUT1:%.+]] = om.constant true
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; MLIR_OUT-DAG: [[OBJ1:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR1]], [[DUT1]]) : (!om.basepath, !om.string, i1) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[LIBS1:%.+]] = om.list_create [[STR1]] : !om.string
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; MLIR_OUT-DAG: [[OBJ1:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR1]], [[DUT1]], [[LIBS1]]) : (!om.basepath, !om.string, i1, !om.list<!om.string>) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[STR2:%.+]] = om.constant "Bar_BlackBox" : !om.string
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; MLIR_OUT-DAG: [[DUT2:%.+]] = om.constant true
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; MLIR_OUT-DAG: [[OBJ2:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR2]], [[DUT2]]) : (!om.basepath, !om.string, i1) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[LIBS2:%.+]] = om.list_create [[STR2]] : !om.string
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; MLIR_OUT-DAG: [[OBJ2:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR2]], [[DUT2]], [[LIBS2]]) : (!om.basepath, !om.string, i1, !om.list<!om.string>) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[STR3:%.+]] = om.constant "Baz_BlackBox" : !om.string
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; MLIR_OUT-DAG: [[DUT3:%.+]] = om.constant true
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; MLIR_OUT-DAG: [[OBJ3:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR3]], [[DUT3]]) : (!om.basepath, !om.string, i1) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT-DAG: [[LIBS3:%.+]] = om.list_create [[STR3]] : !om.string
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; MLIR_OUT-DAG: [[OBJ3:%.+]] = om.object @SitestBlackBoxModulesSchema(%basepath, [[STR3]], [[DUT3]], [[LIBS3]]) : (!om.basepath, !om.string, i1, !om.list<!om.string>) -> !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: om.class.fields [[OBJ1]], [[OBJ2]], [[OBJ3]] : !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>, !om.class.type<@SitestBlackBoxModulesSchema>
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; MLIR_OUT: }
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@ -239,6 +239,7 @@ firrtl.circuit "BasicBlackboxes" attributes {
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firrtl.instance test @DUTBlackbox_1()
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firrtl.instance test @DUTBlackbox_2()
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firrtl.instance layerBlackboxInDesign1 @LayerBlackboxInDesign()
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firrtl.instance blacklistedWithLibsDut @InlineBlackboxWithLibs()
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firrtl.layerblock @A {
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firrtl.instance layerBlackboxInDesign2 @LayerBlackboxInDesign()
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firrtl.instance layerBlackbox @LayerBlackbox()
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@ -298,6 +299,37 @@ firrtl.circuit "BasicBlackboxes" attributes {
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firrtl.extmodule @DUTBlackbox_2() attributes {defname = "DUTBlackbox1"}
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firrtl.extmodule @LayerBlackboxInDesign() attributes {defname = "LayerBlackboxInDesign"}
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firrtl.extmodule @LayerBlackbox() attributes {defname = "LayerBlackbox"}
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// Test blacklisted blackbox with additional libraries - should be included
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firrtl.extmodule @InlineBlackboxWithLibs() attributes {
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annotations = [
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{
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class = "firrtl.transforms.BlackBoxInlineAnno"
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},
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{
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class = "sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation",
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libraries = ["lib1", "lib2"]
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}
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],
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defname = "InlineBlackboxWithLibs"
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}
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// Test non-blacklisted blackbox with additional libraries - should be included
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firrtl.extmodule @BlackboxWithLibs() attributes {
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annotations = [
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{
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class = "sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation",
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libraries = ["lib3", "lib4", "lib5"]
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}
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],
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defname = "BlackboxWithLibs"
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}
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firrtl.module @TestHarness() {
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firrtl.instance inlineBlackboxWithLibs @InlineBlackboxWithLibs()
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firrtl.instance blackboxWithLibs @BlackboxWithLibs()
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firrtl.instance test @TestBlackbox()
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}
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}
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// (1) Class-based metadata ----------------------------------------------------
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@ -306,10 +338,13 @@ firrtl.circuit "BasicBlackboxes" attributes {
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// CHECK-SAME: in %[[moduleName_in:[^:]+]]: !firrtl.string,
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// CHECK-SAME: out %moduleName: !firrtl.string,
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// CHECK-SAME: in %[[inDut_in:[^:]+]]: !firrtl.bool,
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// CHECK-SAME: out %inDut: !firrtl.bool
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// CHECK-SAME: out %inDut: !firrtl.bool,
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// CHECK-SAME: in %[[libraries_in:[^:]+]]: !firrtl.list<string>,
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// CHECK-SAME: out %libraries: !firrtl.list<string>
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// CHECK-SAME: ) {
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// CHECK-NEXT: firrtl.propassign %moduleName, %[[moduleName_in]]
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// CHECK-NEXT: firrtl.propassign %inDut, %[[inDut_in]]
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// CHECK-NEXT: firrtl.propassign %libraries, %[[libraries_in]]
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// CHECK: }
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//
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// CHECK: firrtl.class @SitestBlackBoxMetadata(
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@ -318,61 +353,111 @@ firrtl.circuit "BasicBlackboxes" attributes {
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// CHECK-SAME: out %DUTBlackbox_1_field: !firrtl.class<@SitestBlackBoxModulesSchema(
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// CHECK-SAME: out %LayerBlackboxInDesign_field: !firrtl.class<@SitestBlackBoxModulesSchema(
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// CHECK-SAME: out %LayerBlackbox_field: !firrtl.class<@SitestBlackBoxModulesSchema(
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// CHECK-SAME: out %InlineBlackboxWithLibs_field: !firrtl.class<@SitestBlackBoxModulesSchema(
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// CHECK-SAME: out %BlackboxWithLibs_field: !firrtl.class<@SitestBlackBoxModulesSchema(
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// CHECK-NOT: !firrtl.class<@SitestBlackBoxModulesSchema(
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//
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// CHECK-NEXT: %[[#defname:]] = firrtl.string "TestBlackbox"
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// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool false
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// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]] : !firrtl.list<string>
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// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
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// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
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// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
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// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
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// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
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// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
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// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
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// CHECK-NEXT: firrtl.propassign %TestBlackbox_field, %[[object]]
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//
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// CHECK-NEXT: %[[#defname:]] = firrtl.string "DUTBlackbox2"
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// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool true
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// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]] : !firrtl.list<string>
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// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
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// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %DUTBlackbox_0_field, %[[object]]
|
||||
//
|
||||
// CHECK-NEXT: %[[#defname:]] = firrtl.string "DUTBlackbox1"
|
||||
// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool true
|
||||
// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
|
||||
// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %DUTBlackbox_1_field, %[[object]]
|
||||
//
|
||||
// CHECK-NEXT: %[[#defname:]] = firrtl.string "LayerBlackboxInDesign"
|
||||
// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool true
|
||||
// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
|
||||
// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %LayerBlackboxInDesign_field, %[[object]]
|
||||
//
|
||||
// CHECK-NEXT: %[[#defname:]] = firrtl.string "LayerBlackbox"
|
||||
// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool false
|
||||
// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
|
||||
// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %LayerBlackbox_field, %[[object]]
|
||||
//
|
||||
// CHECK-NEXT: %[[#defname:]] = firrtl.string "InlineBlackboxWithLibs"
|
||||
// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool true
|
||||
// CHECK-NEXT: %[[#lib1:]] = firrtl.string "lib1"
|
||||
// CHECK-NEXT: %[[#lib2:]] = firrtl.string "lib2"
|
||||
// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#lib1]], %[[#lib2]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
|
||||
// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %InlineBlackboxWithLibs_field, %[[object]]
|
||||
//
|
||||
// CHECK-NEXT: %[[#defname:]] = firrtl.string "BlackboxWithLibs"
|
||||
// CHECK-NEXT: %[[#inDutVal:]] = firrtl.bool false
|
||||
// CHECK-NEXT: %[[#lib3:]] = firrtl.string "lib3"
|
||||
// CHECK-NEXT: %[[#lib4:]] = firrtl.string "lib4"
|
||||
// CHECK-NEXT: %[[#lib5:]] = firrtl.string "lib5"
|
||||
// CHECK-NEXT: %[[#libsList:]] = firrtl.list.create %[[#defname]], %[[#lib3]], %[[#lib4]], %[[#lib5]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: %[[object:.+]] = firrtl.object @SitestBlackBoxModulesSchema
|
||||
// CHECK-NEXT: %[[#moduleName:]] = firrtl.object.subfield %[[object]][moduleName_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#moduleName]], %[[#defname:]] : !firrtl.string
|
||||
// CHECK-NEXT: %[[#inDut:]] = firrtl.object.subfield %[[object]][inDut_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#inDut]], %[[#inDutVal]] : !firrtl.bool
|
||||
// CHECK-NEXT: %[[#libraries:]] = firrtl.object.subfield %[[object]][libraries_in]
|
||||
// CHECK-NEXT: firrtl.propassign %[[#libraries]], %[[#libsList]] : !firrtl.list<string>
|
||||
// CHECK-NEXT: firrtl.propassign %BlackboxWithLibs_field, %[[object]]
|
||||
//
|
||||
// CHECK-NOT: firrtl.object
|
||||
|
||||
// (2) JSON file-based metadata ------------------------------------------------
|
||||
//
|
||||
// CHECK: emit.file "test_blackboxes.json" {
|
||||
// CHECK-NEXT{LITERAL}: emit.verbatim "[\0A
|
||||
// CHECK-SAME: \22BlackboxWithLibs\22,\0A
|
||||
// CHECK-SAME: \22LayerBlackbox\22,\0A
|
||||
// CHECK-SAME: \22TestBlackbox\22\0A
|
||||
// CHECK-SAME: \22TestBlackbox\22,\0A
|
||||
// CHECK-SAME: \22lib3\22,\0A
|
||||
// CHECK-SAME: \22lib4\22,\0A
|
||||
// CHECK-SAME: \22lib5\22\0A
|
||||
// CHECK-SAME: ]"
|
||||
// CHECK-NEXT: }
|
||||
//
|
||||
|
|
@ -380,7 +465,9 @@ firrtl.circuit "BasicBlackboxes" attributes {
|
|||
// CHECK-NEXT{LITERAL}: emit.verbatim "[\0A
|
||||
// CHECK-SAME: \22DUTBlackbox1\22,\0A
|
||||
// CHECK-SAME: \22DUTBlackbox2\22,\0A
|
||||
// CHECK-SAME: \22LayerBlackboxInDesign\22\0A
|
||||
// CHECK-SAME: \22LayerBlackboxInDesign\22,\0A
|
||||
// CHECK-SAME: \22lib1\22,\0A
|
||||
// CHECK-SAME: \22lib2\22\0A
|
||||
// CHECK-SAME: ]"
|
||||
// CHECK-NEXT: }
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue