mirror of https://github.com/llvm/circt.git
[Deseq] Add bin flag to enable mux (#8686)
Set the `bin` flag on the `comb.mux` that we insert for enable flip-flops in LLHD's Deseq pass. This allows circt-verilog to preserve the difference between `if (en) q <= d` and `q <= en ? d : q` enables. In the future we'll probably want to have more explicit ops to describe these differences. But adding the `bin` flag causes the pipeline to preserve the property we're interested in for now.
This commit is contained in:
Fabian Schuiki
GitHub
parent
752ccb5218
commit
c43ec9809f
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@ -1110,11 +1110,14 @@ void Deseq::implementRegister(DriveInfo &drive) {
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/*isAsync=*/reset != Value{});
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// If the register has an enable, insert a self-mux in front of the register.
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// Set the `bin` flag on the mux specifically to make up for a subtle
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// difference between a `if (en) q <= d` enable on a register, and a `q <= en
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// ? d : q` enable.
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if (enable) {
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OpBuilder::InsertionGuard guard(builder);
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builder.setInsertionPoint(reg);
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reg.getNextMutable().assign(builder.create<comb::MuxOp>(
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loc, enable, reg.getNext(), reg.getResult()));
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loc, enable, reg.getNext(), reg.getResult(), true));
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}
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// Make the original `llhd.drv` drive the register value unconditionally.
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@ -132,7 +132,7 @@ hw.module @ClockWithEnable(in %clock: i1, in %d: i42, in %en: i1) {
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}
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%3 = llhd.sig %c0_i42 : i42
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// CHECK: [[CLK:%.+]] = seq.to_clock %clock
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// CHECK: [[MUX:%.+]] = comb.mux [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[MUX:%.+]] = comb.mux bin [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[REG]] = seq.firreg [[MUX]] clock [[CLK]] : i42
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// CHECK: llhd.drv {{%.+}}, [[REG]] after {{%.+}} :
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llhd.drv %3, %1 after %0 if %2 : !hw.inout<i42>
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@ -169,7 +169,7 @@ hw.module @ClockWithEnableAndReset(in %clock: i1, in %reset: i1, in %d: i42, in
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}
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%3 = llhd.sig %c0_i42 : i42
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// CHECK: [[CLK:%.+]] = seq.to_clock %clock
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// CHECK: [[MUX:%.+]] = comb.mux [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[MUX:%.+]] = comb.mux bin [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[REG]] = seq.firreg [[MUX]] clock [[CLK]] reset async %reset, %c42_i42 : i42
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// CHECK: llhd.drv {{%.+}}, [[REG]] after {{%.+}} :
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llhd.drv %3, %1 after %0 if %2 : !hw.inout<i42>
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@ -422,7 +422,7 @@ hw.module @ComplexControlFlow(in %clock: i1, in %d: i42) {
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}
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%3 = llhd.sig %c0_i42 : i42
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// CHECK: [[CLK:%.+]] = seq.to_clock %clock
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// CHECK: [[MUX:%.+]] = comb.mux [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[MUX:%.+]] = comb.mux bin [[ER]]#1, [[ER]]#0, [[REG:%.+]] : i42
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// CHECK: [[REG]] = seq.firreg [[MUX]] clock [[CLK]] : i42
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// CHECK: llhd.drv {{%.+}}, [[REG]] after {{%.+}} :
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llhd.drv %3, %1 after %0 if %2 : !hw.inout<i42>
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@ -824,75 +824,75 @@ hw.module @LargeControlFlowRegression(in %clk: i1, in %rstn: i1, in %a: i6, in %
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}
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// CHECK: [[CLK:%.+]] = seq.to_clock %clk
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// CHECK: [[RST:%.+]] = comb.xor %rstn, %true
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#1, [[ER]]#0, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#1, [[ER]]#0, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#3, [[ER]]#2, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#3, [[ER]]#2, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#5, [[ER]]#4, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#5, [[ER]]#4, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#7, [[ER]]#6, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#7, [[ER]]#6, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#9, [[ER]]#8, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#9, [[ER]]#8, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#11, [[ER]]#10, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#11, [[ER]]#10, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#13, [[ER]]#12, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#13, [[ER]]#12, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#15, [[ER]]#14, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#15, [[ER]]#14, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#17, [[ER]]#16, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#17, [[ER]]#16, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#19, [[ER]]#18, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#19, [[ER]]#18, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#21, [[ER]]#20, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#21, [[ER]]#20, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#23, [[ER]]#22, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#23, [[ER]]#22, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#25, [[ER]]#24, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#25, [[ER]]#24, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#27, [[ER]]#26, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#27, [[ER]]#26, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#29, [[ER]]#28, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#29, [[ER]]#28, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#31, [[ER]]#30, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#31, [[ER]]#30, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#33, [[ER]]#32, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#33, [[ER]]#32, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#35, [[ER]]#34, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#35, [[ER]]#34, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#37, [[ER]]#36, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#37, [[ER]]#36, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#39, [[ER]]#38, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#39, [[ER]]#38, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#41, [[ER]]#40, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#41, [[ER]]#40, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#43, [[ER]]#42, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#43, [[ER]]#42, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#45, [[ER]]#44, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#45, [[ER]]#44, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#47, [[ER]]#46, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#47, [[ER]]#46, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#49, [[ER]]#48, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#49, [[ER]]#48, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#51, [[ER]]#50, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#51, [[ER]]#50, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#53, [[ER]]#52, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#53, [[ER]]#52, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#55, [[ER]]#54, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#55, [[ER]]#54, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#57, [[ER]]#56, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#57, [[ER]]#56, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#59, [[ER]]#58, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#59, [[ER]]#58, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#61, [[ER]]#60, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#61, [[ER]]#60, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#63, [[ER]]#62, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#63, [[ER]]#62, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#65, [[ER]]#64, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#65, [[ER]]#64, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#67, [[ER]]#66, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#67, [[ER]]#66, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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// CHECK: [[TMP:%.+]] = comb.mux [[ER]]#69, [[ER]]#68, {{%.+}}
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// CHECK: [[TMP:%.+]] = comb.mux bin [[ER]]#69, [[ER]]#68, {{%.+}}
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// CHECK: seq.firreg [[TMP]] clock [[CLK]] reset async [[RST]], %c0_i15
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llhd.drv %mem0, %1#0 after %0 if %1#1 : !hw.inout<i15>
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llhd.drv %mem1, %1#2 after %0 if %1#3 : !hw.inout<i15>
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@ -52,7 +52,7 @@ endmodule
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// CHECK-LABEL: hw.module @Enable(
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module Enable(input logic clock, input logic enable, input int d, output int q);
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// CHECK: [[CLK:%.+]] = seq.to_clock %clock
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// CHECK: [[MUX:%.+]] = comb.mux %enable, %d, [[REG:%.+]] : i32
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// CHECK: [[MUX:%.+]] = comb.mux bin %enable, %d, [[REG:%.+]] : i32
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// CHECK: [[REG]] = seq.firreg [[MUX]] clock [[CLK]] : i32
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// CHECK: hw.output [[REG]]
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always @(posedge clock) if (enable) q <= d;
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@ -61,7 +61,7 @@ endmodule
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// CHECK-LABEL: hw.module @ResetAndEnable(
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module ResetAndEnable(input logic clock, input logic reset, input logic enable, input int d, output int q);
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// CHECK: [[CLK:%.+]] = seq.to_clock %clock
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// CHECK: [[MUX:%.+]] = comb.mux %enable, %d, [[REG:%.+]] : i32
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// CHECK: [[MUX:%.+]] = comb.mux bin %enable, %d, [[REG:%.+]] : i32
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// CHECK: [[REG]] = seq.firreg [[MUX]] clock [[CLK]] reset async %reset, %c42_i32 : i32
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// CHECK: hw.output [[REG]]
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always @(posedge clock, posedge reset) if (reset) q <= 42; else if (enable) q <= d;
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@ -0,0 +1,23 @@
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// RUN: circt-verilog %s | circt-opt --lower-seq-to-sv --export-verilog | FileCheck %s
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// REQUIRES: slang
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// Internal issue in Slang v3 about jump depending on uninitialised value.
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// UNSUPPORTED: valgrind
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// Ensure we can round-trip the following two different flavors of enables on a
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// register and have them come out unchanged. These have subtly different
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// semantics when `en` is X, which must be preserved in order to satisfy logical
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// equivalence checks.
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// CHECK-LABEL: module Foo
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module Foo (input logic clk, en, d, output logic qa, qb);
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// CHECK: always @(posedge clk)
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always @(posedge clk) begin
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// CHECK: if (en)
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// CHECK: [[QA:qa.*]] <= d;
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if (en)
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qa <= d;
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// CHECK: [[QB:qb.*]] <= en ? d : [[QB]];
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qb <= en ? d : qb;
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end
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endmodule
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