mirror of https://github.com/llvm/circt.git
[FIRRTL] FRT: support creating 0-valued enums (#8772)
This adds the ability to the FullResetTransform to create enumeration values which are 0. When the enumeration has a valid variant that is encoded as a 0, we create this value using the FEnumCreateOp. If there is no valid variant with the value 0, we create a constant 0 and bitcast it to the enumeration type.
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@ -141,6 +141,21 @@ static Value createZeroValue(ImplicitLocOpBuilder &builder, FIRRTLBaseType type,
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return builder.create<ConstantOp>(
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type, APInt::getZero(type.getWidth().value_or(1)));
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})
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.Case<FEnumType>([&](auto type) -> Value {
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// There might not be a variant that corresponds to 0, in which case
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// we have to create a 0 value and bitcast it to the enum.
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if (type.getNumElements() != 0 &&
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type.getElement(0).value.getValue().isZero()) {
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const auto &element = type.getElement(0);
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auto value = createZeroValue(builder, element.type, cache);
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return builder.create<FEnumCreateOp>(type, element.name, value);
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}
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auto value = builder.create<ConstantOp>(
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UIntType::get(builder.getContext(), type.getBitWidth(),
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/*isConst=*/true),
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APInt::getZero(type.getBitWidth()));
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return builder.create<BitCastOp>(type, value);
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})
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.Case<BundleType>([&](auto type) {
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auto wireOp = builder.create<WireOp>(type);
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for (unsigned i = 0, e = type.getNumElements(); i < e; ++i) {
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@ -495,6 +495,12 @@ firrtl.circuit "Top" {
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// CHECK: firrtl.matchingconnect %10, %c0_ui8_0
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// CHECK: %reg_vector = firrtl.regreset %clock, %reset, %6
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%reg_vector = firrtl.reg %clock : !firrtl.clock, !firrtl.vector<uint<8>, 4>
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// CHECK: [[ENUMCREATE:%[0-9]+]] = firrtl.enumcreate a(%c0_ui0) : (!firrtl.const.uint<0>) -> !firrtl.const.enum<a>
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// CHECK: %reg_enum_0 = firrtl.regreset %clock, %reset, [[ENUMCREATE]] : !firrtl.clock, !firrtl.asyncreset, !firrtl.const.enum<a>, !firrtl.enum<a>
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%reg_enum_0 = firrtl.reg %clock : !firrtl.clock, !firrtl.enum<a>
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// CHECK: [[BITCAST:%[0-9]+]] = firrtl.bitcast %c0_ui1 : (!firrtl.const.uint<1>) -> !firrtl.const.enum<a = 1>
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// CHECK: %reg_enum_1 = firrtl.regreset %clock, %reset, [[BITCAST]] : !firrtl.clock, !firrtl.asyncreset, !firrtl.const.enum<a = 1>, !firrtl.enum<a = 1>
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%reg_enum_1 = firrtl.reg %clock : !firrtl.clock, !firrtl.enum<a = 1>
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}
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}
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