[RTGTest] Add integer register type API (#8141)

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Martin Erhart 2025-02-03 07:59:22 +00:00 committed by GitHub
parent 518f3a1906
commit deb88ba5ec
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5 changed files with 37 additions and 2 deletions

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@ -31,6 +31,12 @@ MLIR_CAPI_EXPORTED bool rtgtestTypeIsACPU(MlirType type);
/// Creates an RTGTest CPU type in the context.
MLIR_CAPI_EXPORTED MlirType rtgtestCPUTypeGet(MlirContext ctxt);
/// If the type is an RTGTest IntegerRegisterType.
MLIR_CAPI_EXPORTED bool rtgtestTypeIsAIntegerRegister(MlirType type);
/// Creates an RTGTest IntegerRegisterType in the context.
MLIR_CAPI_EXPORTED MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt);
// Immediates.
//===----------------------------------------------------------------------===//

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@ -88,11 +88,13 @@ with Context() as ctx, Location.unknown():
labelTy = rtg.LabelType.get()
setTy = rtg.SetType.get(indexTy)
bagTy = rtg.BagType.get(indexTy)
ireg = rtgtest.IntegerRegisterType.get()
seq = rtg.SequenceOp('seq')
Block.create_at_start(seq.bodyRegion, [sequenceTy, labelTy, setTy, bagTy])
Block.create_at_start(seq.bodyRegion,
[sequenceTy, labelTy, setTy, bagTy, ireg])
# CHECK: rtg.sequence @seq
# CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>):
# CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>, %{{.*}}: !rtgtest.ireg):
print(m)
with Context() as ctx, Location.unknown():

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@ -30,6 +30,14 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) {
},
nb::arg("self"), nb::arg("ctxt") = nullptr);
mlir_type_subclass(m, "IntegerRegisterType", rtgtestTypeIsAIntegerRegister)
.def_classmethod(
"get",
[](nb::object cls, MlirContext ctxt) {
return cls(rtgtestIntegerRegisterTypeGet(ctxt));
},
nb::arg("self"), nb::arg("ctxt") = nullptr);
mlir_type_subclass(m, "Imm12Type", rtgtestTypeIsAImm12)
.def_classmethod(
"get",

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@ -32,6 +32,14 @@ MlirType rtgtestCPUTypeGet(MlirContext ctxt) {
return wrap(CPUType::get(unwrap(ctxt)));
}
bool rtgtestTypeIsAIntegerRegister(MlirType type) {
return isa<IntegerRegisterType>(unwrap(type));
}
MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) {
return wrap(IntegerRegisterType::get(unwrap(ctxt)));
}
// Immediates.
//===----------------------------------------------------------------------===//

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@ -21,6 +21,16 @@ static void testCPUType(MlirContext ctx) {
mlirTypeDump(cpuTy);
}
static void testIntegerRegisterType(MlirContext ctx) {
MlirType iregTy = rtgtestIntegerRegisterTypeGet(ctx);
// CHECK: is_ireg
fprintf(stderr,
rtgtestTypeIsAIntegerRegister(iregTy) ? "is_ireg\n" : "isnot_ireg\n");
// CHECK: !rtgtest.ireg
mlirTypeDump(iregTy);
}
static void testCPUAttr(MlirContext ctx) {
MlirAttribute cpuAttr = rtgtestCPUAttrGet(ctx, 3);
@ -322,6 +332,7 @@ int main(int argc, char **argv) {
mlirDialectHandleLoadDialect(mlirGetDialectHandle__rtgtest__(), ctx);
testCPUType(ctx);
testIntegerRegisterType(ctx);
testCPUAttr(ctx);
testRegisters(ctx);
testImmediates(ctx);