mirror of https://github.com/llvm/circt.git
[RTGTest] Add integer register type API (#8141)
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@ -31,6 +31,12 @@ MLIR_CAPI_EXPORTED bool rtgtestTypeIsACPU(MlirType type);
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/// Creates an RTGTest CPU type in the context.
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MLIR_CAPI_EXPORTED MlirType rtgtestCPUTypeGet(MlirContext ctxt);
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/// If the type is an RTGTest IntegerRegisterType.
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MLIR_CAPI_EXPORTED bool rtgtestTypeIsAIntegerRegister(MlirType type);
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/// Creates an RTGTest IntegerRegisterType in the context.
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MLIR_CAPI_EXPORTED MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt);
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// Immediates.
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//===----------------------------------------------------------------------===//
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@ -88,11 +88,13 @@ with Context() as ctx, Location.unknown():
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labelTy = rtg.LabelType.get()
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setTy = rtg.SetType.get(indexTy)
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bagTy = rtg.BagType.get(indexTy)
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ireg = rtgtest.IntegerRegisterType.get()
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seq = rtg.SequenceOp('seq')
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Block.create_at_start(seq.bodyRegion, [sequenceTy, labelTy, setTy, bagTy])
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Block.create_at_start(seq.bodyRegion,
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[sequenceTy, labelTy, setTy, bagTy, ireg])
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# CHECK: rtg.sequence @seq
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# CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>):
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# CHECK: (%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>, %{{.*}}: !rtgtest.ireg):
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print(m)
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with Context() as ctx, Location.unknown():
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@ -30,6 +30,14 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) {
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr);
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mlir_type_subclass(m, "IntegerRegisterType", rtgtestTypeIsAIntegerRegister)
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.def_classmethod(
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"get",
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[](nb::object cls, MlirContext ctxt) {
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return cls(rtgtestIntegerRegisterTypeGet(ctxt));
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr);
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mlir_type_subclass(m, "Imm12Type", rtgtestTypeIsAImm12)
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.def_classmethod(
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"get",
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@ -32,6 +32,14 @@ MlirType rtgtestCPUTypeGet(MlirContext ctxt) {
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return wrap(CPUType::get(unwrap(ctxt)));
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}
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bool rtgtestTypeIsAIntegerRegister(MlirType type) {
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return isa<IntegerRegisterType>(unwrap(type));
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}
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MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) {
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return wrap(IntegerRegisterType::get(unwrap(ctxt)));
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}
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// Immediates.
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//===----------------------------------------------------------------------===//
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@ -21,6 +21,16 @@ static void testCPUType(MlirContext ctx) {
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mlirTypeDump(cpuTy);
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}
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static void testIntegerRegisterType(MlirContext ctx) {
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MlirType iregTy = rtgtestIntegerRegisterTypeGet(ctx);
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// CHECK: is_ireg
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fprintf(stderr,
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rtgtestTypeIsAIntegerRegister(iregTy) ? "is_ireg\n" : "isnot_ireg\n");
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// CHECK: !rtgtest.ireg
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mlirTypeDump(iregTy);
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}
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static void testCPUAttr(MlirContext ctx) {
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MlirAttribute cpuAttr = rtgtestCPUAttrGet(ctx, 3);
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@ -322,6 +332,7 @@ int main(int argc, char **argv) {
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mlirDialectHandleLoadDialect(mlirGetDialectHandle__rtgtest__(), ctx);
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testCPUType(ctx);
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testIntegerRegisterType(ctx);
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testCPUAttr(ctx);
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testRegisters(ctx);
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testImmediates(ctx);
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