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[ImportVerilog] Support packed structs in `inside` operator (#8545) 

Fixes #8440.
This commit is contained in:
Annu Singh 2025-06-20 22:37:08 +05:30 committed by GitHub
parent de46d1dd08
commit e21b0d41b6
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2 changed files with 14 additions and 1 deletions
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3
lib/Conversion/ImportVerilog/Expressions.cpp
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@ -637,7 +637,7 @@ struct RvalueExprVisitor {
cond = builder.create<moore::AndOp>(loc, leftValue, rightValue);
} else {
// Handle expressions.
if (!listExpr->type->isSimpleBitVector()) {
if (!listExpr->type->isIntegral()) {
if (listExpr->type->isUnpackedArray()) {
mlir::emitError(
loc, "unpacked arrays in 'inside' expressions not supported");
@ -647,6 +647,7 @@ struct RvalueExprVisitor {
loc, "only simple bit vectors supported in 'inside' expressions");
return {};
}
auto value = context.convertToSimpleBitVector(
context.convertRvalueExpression(*listExpr));
if (!value)

12
test/Conversion/ImportVerilog/basic.sv
View File

@ -1545,6 +1545,18 @@ module Expressions;
// CHECK: moore.struct_create [[TMP0]], [[TMP1]] : !moore.i32, !moore.i32 -> struct<{a: i32, b: i32}>
struct0 = '{43, 9002};
// CHECK: [[TMP0:%.+]] = moore.constant 43 : i32
// CHECK: [[TMP1:%.+]] = moore.sext [[TMP0]] : i32 -> i64
// CHECK: [[TMP2:%.+]] = moore.read %struct0 : <struct<{a: i32, b: i32}>>
// CHECK: [[TMP3:%.+]] = moore.conversion [[TMP2]] : !moore.struct<{a: i32, b: i32}> -> !moore.i64
// CHECK: [[TMP4:%.+]] = moore.wildcard_eq [[TMP1]], [[TMP3]] : i64 -> i1
// CHECK: [[TMP5:%.+]] = moore.zext [[TMP4]] : i1 -> i32
// CHECK: [[TMP6:%.+]] = moore.conversion [[TMP5]] : !moore.i32 -> !moore.l32
// CHECK: [[TMP7:%.+]] = moore.conversion [[TMP6]] : !moore.l32 -> !moore.i32
// CHECK: moore.blocking_assign %c, [[TMP7]] : i32
c = 43 inside {struct0};
// CHECK: [[TMP0:%.+]] = moore.constant 44
// CHECK: [[TMP1:%.+]] = moore.constant 9003
// CHECK: moore.struct_create [[TMP0]], [[TMP1]] : !moore.i32, !moore.i32 -> ustruct<{a: i32, b: i32}>