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[ImportVerilog] Distinguish the index up or down on the range selection. (#7280)

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Hailong Sun 2024-07-10 13:21:04 +08:00 committed by GitHub
parent 2671b3636b
commit e2b4cb9c72
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2 changed files with 41 additions and 1 deletions
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32
lib/Conversion/ImportVerilog/Expressions.cpp
View File

@ -434,7 +434,23 @@ struct RvalueExprVisitor {
<< slang::ast::toString(expr.getSelectionKind()) << "kind";
return {};
}
} else if (expr.getSelectionKind() ==
slang::ast::RangeSelectionKind::IndexedDown) {
// IndexedDown: arr[7-:8]. It's equivalent to arr[7:0] or arr[0:7]
// depending on little endian or bit endian. No matter which situation,
// the low bit must be "0".
auto minuend = context.convertRvalueExpression(expr.left());
auto minuendType = cast<moore::UnpackedType>(minuend.getType());
auto intType = moore::IntType::get(context.getContext(),
minuendType.getBitSize().value(),
minuendType.getDomain());
auto sliceWidth =
expr.right().constant->integer().as<uint64_t>().value() - 1;
auto subtraction =
builder.create<moore::ConstantOp>(loc, intType, sliceWidth);
lowBit = builder.create<moore::SubOp>(loc, minuend, subtraction);
} else
// IndexedUp: arr[0+:8]. "0" is the low bit, "8" is the bits slice width.
lowBit = context.convertRvalueExpression(expr.left());
if (!type || !value || !lowBit)
@ -653,7 +669,23 @@ struct LvalueExprVisitor {
<< slang::ast::toString(expr.getSelectionKind()) << "kind";
return {};
}
} else if (expr.getSelectionKind() ==
slang::ast::RangeSelectionKind::IndexedDown) {
// IndexedDown: arr[7-:8]. It's equivalent to arr[7:0] or arr[0:7]
// depending on little endian or bit endian. No matter which situation,
// the low bit must be "0".
auto minuend = context.convertRvalueExpression(expr.left());
auto minuendType = cast<moore::UnpackedType>(minuend.getType());
auto intType = moore::IntType::get(context.getContext(),
minuendType.getBitSize().value(),
minuendType.getDomain());
auto sliceWidth =
expr.right().constant->integer().as<uint64_t>().value() - 1;
auto subtraction =
builder.create<moore::ConstantOp>(loc, intType, sliceWidth);
lowBit = builder.create<moore::SubOp>(loc, minuend, subtraction);
} else
// IndexedUp: arr[0+:8]. "0" is the low bit, "8" is the bits slice width.
lowBit = context.convertRvalueExpression(expr.left());
if (!type || !value || !lowBit)

10
test/Conversion/ImportVerilog/basic.sv
View File

@ -476,7 +476,9 @@ module Expressions;
// CHECK: [[TMP2:%.+]] = moore.constant 1 : i32
// CHECK: [[TMP3:%.+]] = moore.read %a : i32
// CHECK: [[TMP4:%.+]] = moore.mul [[TMP2]], [[TMP3]] : i32
// CHECK: moore.extract [[TMP1]] from [[TMP4]] : l32, i32 -> l1
// CHECK: [[TMP5:%.+]] = moore.constant 0 : i32
// CHECK: [[TMP6:%.+]] = moore.sub [[TMP4]], [[TMP5]] : i32
// CHECK: moore.extract [[TMP1]] from [[TMP6]] : l32, i32 -> l1
c = vec_1[1*a-:1];
// CHECK: [[TMP1:%.+]] = moore.read %arr : uarray<3 x uarray<6 x i4>>
// CHECK: [[TMP2:%.+]] = moore.constant 3 : i32
@ -504,6 +506,12 @@ module Expressions;
// CHECK: [[X_READ:%.+]] = moore.read %x : i1
// CHECK: moore.extract_ref %vec_1 from [[X_READ]] : <l32>, i1 -> <l1>
vec_1[x] = y;
// CHECK: [[CONST_15:%.+]] = moore.constant 15 : i32
// CHECK: [[CONST_2:%.+]] = moore.constant 2 : i32
// CHECK: [[SUB:%.+]] = moore.sub [[CONST_15]], [[CONST_2]] : i32
// CHECK: moore.extract_ref %vec_1 from [[SUB]] : <l32>, i32 -> <l3>
vec_1[15-:3] = y;
//===------------------------------------------------------------------===//
// Unary operators