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Introduce a firrtl.invalid operation and give firrtl.add nicer syntax.

This commit is contained in:
Chris Lattner 2020-03-07 23:10:55 -08:00
parent 6dfa2793f0
commit ef84a84a6f
2 changed files with 43 additions and 7 deletions
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36
include/spt/Dialect/FIRRTL/IR/FIRRTL.td
View File

@ -94,15 +94,39 @@ def DoneOp : FIRRTLOp<"done", [Terminator]> {
let arguments = (ins);
}
def FIRRTLInvalid : FIRRTLOp<"invalid", [NoSideEffect]> {
let summary = "Invalid operation";
let description = [{
Invalidate Operation:
```
%result = firrt.invalid : i8
```
The invalid operation produces a value of unspecified value. Drivers may
be attached to it with `firrtl.connect`.
}];
let arguments = (ins OptionalAttr<StrAttr>:$name);
let results = (outs AnyType:$result);
// TODO: Print '$name' more nicely. This breaks the asmparser tho.
let assemblyFormat = [{
attr-dict `:` type($result)
}];
}
//===----------------------------------------------------------------------===//
// Primitive Operations
//===----------------------------------------------------------------------===//
// TODO: Should this be split out to addu/adds?
def FIRRTLAddOp : FIRRTLOp<"add", [Commutative]> {
def FIRRTLAddOp : FIRRTLOp<"add", [Commutative, NoSideEffect]> {
let summary = "Add operations";
let description = [{
Add Operation: x = add (y, z)
Add Operation:
```
%result = firrt.add %lhs, %rhs "name" : (t1, t2) -> t3
```
The two options are:
* add(UInt, UInt) -> UInt
@ -112,8 +136,14 @@ def FIRRTLAddOp : FIRRTLOp<"add", [Commutative]> {
The add operation result is the sum of e1 and e2 without loss of precision.
}];
let arguments = (ins AnyType:$lhs, AnyType:$rhs);
let arguments = (ins AnyType:$lhs, AnyType:$rhs, OptionalAttr<StrAttr>:$name);
let results = (outs AnyType:$result);
// TODO: Print '$name' more nicely. This breaks the asmparser tho.
let assemblyFormat = [{
$lhs `,` $rhs attr-dict `:`
`(` type($lhs) `,` type($rhs) `)` `->` type($result)
}];
}
#endif // FIRRTL_OPS

14
test/firrtl/test.mlir
View File

@ -30,8 +30,12 @@ firrtl.circuit "Top" {
%0 = "firrtl.output"() {name = "out"} : () -> !firrtl.uint
%1 = "firrtl.input"() {name = "b"} : () -> ui32
%2 = "firrtl.input"() {name = "d"} : () -> ui16
%3 = "firrtl.add"(%1, %2) : (ui32, ui16) -> ui32
"firrtl.connect"(%0, %3) : (!firrtl.uint, ui32) -> ()
%3 = firrtl.add %1, %2 : (ui32, ui16) -> ui32
%4 = firrtl.invalid {name = "Name"} : ui16
%5 = firrtl.add %3, %4 : (ui32, ui16) -> ui32
"firrtl.connect"(%0, %5) : (!firrtl.uint, ui32) -> ()
}
}
@ -40,8 +44,10 @@ firrtl.circuit "Top" {
// CHECK-NEXT: %0 = "firrtl.output"() {name = "out"} : () -> !firrtl.uint
// CHECK-NEXT: %1 = "firrtl.input"() {name = "b"} : () -> ui32
// CHECK-NEXT: %2 = "firrtl.input"() {name = "d"} : () -> ui16
// CHECK-NEXT: %3 = "firrtl.add"(%1, %2) : (ui32, ui16) -> ui32
// CHECK-NEXT: "firrtl.connect"(%0, %3) : (!firrtl.uint, ui32) -> ()
// CHECK-NEXT: %3 = firrtl.add %1, %2 : (ui32, ui16) -> ui32
// CHECK-NEXT: %4 = firrtl.invalid {name = "Name"} : ui16
// CHECK-NEXT: %5 = firrtl.add %3, %4 : (ui32, ui16) -> ui32
// CHECK-NEXT: "firrtl.connect"(%0, %5) : (!firrtl.uint, ui32) -> ()
// CHECK-NEXT: }
// CHECK-NEXT: }