* Add lowering for AssertProperty operations
* removed nl at start of file
* sorted cmake and removed unreachable branches
* Removed useless wire in test + removed symbol from hbr compreg
This is the first PR in a longer chain that adds basic SV support to
CIRCT.
Add the Slang Verilog frontend as a CIRCT dependency. This will be the
foundation for CIRCT's Verilog parsing, elaboration, type checking, and
lowering to the core dialects. By default, Slang is built as a static
library from scratch, which is then linked into the new `ImportVerilog`
conversion. Alternatively, CIRCT can also be linked against a local
Slang installation provided by the system.
Add the `ImportVerilog` conversion library. This library statically
links in the Slang dependency and wraps it in an exception-safe,
LLVM-style API. Currently this only consists of the `getSlangVersion`
function and the necessary linking flags to get it to link statically
against Slang.
Add the `circt-verilog` tool, which will provide a fully-flegded
interface to the new `ImportVerilog` library. Later on we'll also add an
MLIR translation library for single-file SV import. But in general, SV
builds take a lot of command line options (macros, search paths, etc.)
and multiple input files, which is why we have a dedicated tool. All the
tool does at the moment is print the linked Slang version. More to come.
Note that this intentionally links against **version 3** of Slang. Newer
versions are available -- 4 and 5 as of this commit -- but they rely on
fairly new C++ compiler features that didn't work out of the box in our
CI images. We'll eventually want to upgrade, but for now Slang 3 is
sufficient to get the ball rolling.
See https://github.com/MikePopoloski/slang for details on Slang.
Co-authored-by: ShiZuoye <albertethon@163.com>
Co-authored-by: hunterzju <hunter_ht@zju.edu.cn>
Co-authored-by: 孙海龙 <hailong.sun@terapines.com>
* Added missing tool in integration test
* Fixed formatting
* Fixed whitespace issue
* Fixed typo in VerilogGeneration.md
* Added skeleton for btor2 lowering pass
* added pattern match skeleton to lowering pass
* Added initial emission of inputs and hw::constant ops
* added constant emission
* added emission for most operations and final assertion
* Added support for muxes, assumptions and wire aliases
* Added support for inputs in btor2
* fixed bug in input generation
* added support for missing comb operations
* Changed input registration to allow for booleans
* Made input type check more robust
* WIP register state transition system generation
* Added support for registers
* refactored hardcoded string
* added names to btor2 states
* Added state initialization support
* Removed state initializer, it should be a firrtl construct and not a btor one
* Removed temporary file emission
* Added back accidentally removed btor2 string printing
* Ran clang-format
* Ran clang-format
* WIP refactored typeswitch
* refactored giant type switch
* Made all string litterals constexpr
* attempting to fix sanity check
* fixed variable name typo
* Attempting to satisfy clang-tidy
* renamed things to make clang happy
* inlined useless helper methods
* Clarified the necessity of important data structures in comments
* fixed formatting
* Changed pass into a Conversion pass
* refactored helper methods
* Checked for case where next is a port when emitted transitions
* Added newline at EOF
* Inherited visitors instead of using a big typeswitch
* Throw an error for unsupported ops and explicitly ignore the rest
* Removed unnecessary functions and refactored runOnOperation
* Fixed formatting
* Attempted to add some test
* Added in ops that weren't covered by visitors
* Added in missing declaration in header
* Included pass in CAPI CmakeLists
* Added infrastructure for btor integration tests
* Revert "Added infrastructure for btor integration tests"
This reverts commit a5ec3da4ec.
* various nitpicking comments accounted for
* used generalized ids for btor2 testcase
* fixed typo in test
* updated test and found small bug
* clang-format
* added support for arbitrary resets
* Updated test to reflect new handling of reset
* Switched to a DFS strategy for emission
* Updated test to align with preemission of register declarations
* Removed gratuitous lookups.
* inlined a bunch of string constatns
* removed certain silent fails and added out of order test
This PR moves the conversion of FIRRTL-specific `seq` ops to their own conversion pass, `SeqToSV`.
The existing register & memory lowering passes are packaged as re-usable utilities to keep them available as individual transformations.
Both the memory and register lowering utilities are packaged into a single parallelized lowering.
#5577, #5575
Re. the lowering; `verif.print` lowers directly to a `sv.fwrite` via. inspection of its source operand (which is expected to be a `verif.format_verilog_string`). The source `format_verilog_string` is `not` deleted in the process (there may be other users). However, i marked `verif.format_verilog_string` as `Pure` meaning that it'll get removed if `canonicalize` is run after `lower-verif-to-sv` and there are no more users of the result.
It's expected that `verif.print` will reside inside *something* that eventually lowers to a procedural SV region, if one is going the SV route. I'd imagine that most users will embed `verif.print` inside `hw.triggered` regions.
Here's a stab at the `hw.triggered` operation.
I think the main issue is to decide where to place the lowering. AFAICT, the closest we have to a "hw to sv" conversion pass is `hw-legalize-modules` (which really should be named to `sv-legalize-modules` seeing as it's lowering away HW constructs in favor of SV constructs).
I chose to introduce a new pass - `lower-hw-to-sv` which could serve as a clear home for these kinds of lowerings (maybe some things in `HWLegalizeModules` could be moved to here?).
Lastly, just went with a simple assembly format. If people would like to see something more fancy, e.g. an initializer-list style format with an elided entry block:
> `hw.triggered postedge %t (%a0 : i32 = %in) { ...`
let me know.
This commit adds a lowering of DC operation to a combination of
`comb,seq` and `hw` operations. The implementations are identical to
those of the `handshake` dialect (i.e. `handshake-to-hw` sans the
arithmetic operations).
- ESI-typed I/O
- DC buffers lower to ESI buffers
- This is just a temporary solution. I anticipate more complexity here
in the future when we want to do more with the FIFOs that connect
DC circuits.
- In case the IR contains DC operations that need to be clocked (fork, buffer),
there must exist a clock and reset signal in the parent `FunctionLike`
operation. These arguments are to be marked with a `dc.clock` and `dc.reset`
attribute, respectively.
- Only a single integration test for now. Will add more once #5297 lands
(allows us to do some high-level tests through handshake).
... progressive lowering of handshake!
This obviously requires a future addition of an `arith-to-comb/hw` pass to map arith stuff to comb/external hardware/pipelines, ...
Removes the handshake to FIRRTL lowering pass.
Also:
* All handshake integration tests now run through the handshake to HW pass (thanks to 936db150)
* Some changes were required to the handshake cocotb test runner, seeing as struct are not flattened in HandshakeToHW.
Add two passes to lower a design to a software model.
The `LowerClocksToFuncs` pass outlines all `arc.clock_tree` and
`arc.passthrough` operations into separate MLIR functions. This
conceptually converts clocks from being a signal in the design into a
function that can be called in order to execute the state update
triggered by that clock.
The `LowerArcToLLVM` conversion pass does exactly as it says: it sets up
a dialect conversion from Arc and the core CIRCT dialects to Func/SCF,
and from there to the LLVM dialect.
Also add an output format option to the arcilator tool that allows for
the direct emission of LLVM IR (as opposed to the MLIR's LLVM dialect).
Co-authored-by: Martin Erhart <maerhart@outlook.com>
Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
Add an experimental pass to convert operations in the Comb dialect to
their equivalent in the Arith dialect. The pass isn't used anywhere yet,
but conversion to Arith allows all canonicalizations defined on that
dialect to take effect before mapping things to LLVM to generate a
software model.
Co-authored-by: Martin Erhart <maerhart@outlook.com>
Add the `ConvertToArcs` conversion which collects the combinational
operations in a module body, divides them into distinct sets split along
registers and a few other potentially state-holding operations, and
outlines these sets into arc definitions, inserting an `arc.state` op in
place of the original combinational ops.
Note that this merely replaces logic and registers with arc invocations,
but keeps the module hierarchy intact.
Co-authored-by: Martin Erhart <maerhart@outlook.com>
Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
This is a fairly straight-forward transformation since the brunt of the
work of detecting which values will be registered in a given pipeline
stage has already been performed by a prior pass.
This pass simply elaborates the `pipeline.stage.register` operations
into `seq.compreg` operations and stitches up the circuit.
* [ExportChiselInterface] Basic infrastructure for Chisel Interface file emission
This commit adds a pass for FIRRTL that generates a Scala file with a module
class that represents the interface for the top module of the FIRRTL circuit.
This is to support the development of separable compilation of FIRRTL circuits.
The details about linking circuits together are to be determined. The generated
Scala module extends ExtModule, although a new module class may be introduced
in the future.
This representation and conversion aren't being used, and never
connected to Verilog output. The newer PipelineWhileOp could subsume
this use-case, and further evolution is coming to this dialect, so it
seems like a good time to clean out the older parts that aren't used.
It is probably fair to conclude that naming this dialect `StaticLogic` has been a pain point for a while. This commit proposes a dialect renaming to `Pipeline`, for a couple of reaons:
1. So far, we've only been working with pipeline abstractions within this dialect.
2. Pipeline representations aren't necessarily statically scheduled - we plan on adding switches to select between latency sensitive and latency insensitive lowerings of pipelines.
This name change does not preclude renamings in the future if we want to fit more stuff into this dialect. Personally, i think it is prudent to maintain a dialect name which reflects what's actually being done within the dialect, as well as the (near/mid/"someone actually intends to work on this"-term) future plans for the dialect.
Moves Comb to LLVM and HW to LLVM conversions out of the LLHDToLLVM pass and into their own dedicated lowering passes, as proposed in #3539.
The methods convertToLLVMEndianess and llvmIndexOfStructField are also encapsulated here within a HWToLLVMEndianessConverter class, in order to allow easier re-use between different passes.
This commit represents a lowering pass for converting a Calyx control schedule (seq/if/while/enable) into an FSM representation. The FSM is embedded within the Calyx component, and references both the group symbols and cell SSA values.
The lowering method is a fairly straight forward conversion, which leaves plenty of canonicalization opportunities to remove redundant states in the generated FSM. However, doing it as presented in this PR lends itself to some very clean code (which I prefer, rather than prematurely optimizing during lowering) as well as meaningful naming of states (which i think is fairly important).
This initial commit handles building of the top-level hw.module when converting a handshake.func operation. All handshake modules are created as external hw modules. By doing so, follow-up commits may gradually implement each of the handshake operations using RTL dialect logic.
To transition from FIRRTL bundles with explicit ready/valid/data bundles, this commit relies on ESI channels for handshake module I/O as well as the top-level I/O.
Some changes to the flow are that:
- We're no longer inlining the handshake operations into the hw module. Instead, we maintain a value mapping from SSA values in the handshake.func to those in the hw.module, and maintain this using BackedgeBuilder operations. In general, an approach is taken of maintaining state outside the IR instead of inside the IR.
This is just the first commit in the process of transitioning away from FIRRTL for lowering Handshake operations; transitioning to be ESI based should hopefully also create a good basis for composing Handshake circuits with other parts of future HLS and CIRCT infrastructure.
Currently, the Moore frontend-compiler parses SystemVerilog, lowers the AST to Moore MIR, and then generates HW/Comb/LLHD code which it forwards to CIRCT.
This new Moore dialect aims to move the MIR into CIRCT to benefit from the CIRCT/MLIR infrastructure. In the long-run also the parser and AST can be implemented to have a complete SystemVerilog frontend natively in CIRCT.
The purpose of Moore MIR in the lowering chain is to make all the implicit things (e.g., type casts) in SystemVerilog explicit to ease further lowering to HW/Comb/LLHD.
* Revert "Revert "[StaticLogic] Add conversion pass for Affine loop nests. (#2157)""
This reverts commit 0ce0e99b7c.
The new pass wassing missing a CMake dependency on generated files.
This is just the start of a pass, but this is enough to use the
scheduling tools and build a pipeline. At the moment, this doesn't
make use of the schedule, it just sets up a loop template. This is
just enough to lower a single loop and generate the appropriate
induction variable increments. Checkpointing here before moving any
further.
After this, I plan to add a helper class to this pass to answer the
questions we will need to flesh out createStaticLogicPipeline.
My goal is to take something as simple as this and start threading it
through the Calyx lowering to get a very thin path working before
adding support for more cases.
Co-authored-by: Julian Oppermann <oppermann@esa.tu-darmstadt.de>
* [LLHD] Add start of RTL to LLHD conversion pass.
* Add basic support for converting RTL modules to LLHD entities.
* Switch implementation to use DialectConversion framework.
* Update EntityOp verification.
The verifyType method now uses the type attribute exclusively instead
of looking at the op. If the op was in fact invalid, verifyType could
crash before the verifier got a chance to catch it.
* Add a type converter and use it in RTL module conversion.
This replaces how the entity type is constructed, and is used to
re-map the RTL module's block arguments into the newly created
entity.
* Add conversion for RTL module's output terminator op.
* Clean up comments and error conditions.
* Add RTL to LLHD conversion error checks.
* Final clean ups.
* Implement a basic conversion pass for FIRRTL modules to their
equivalent LLHD entity counterpart. Any operation in the FIRRTL module
will cause the pass to fail. Handles only trivial ports (integers,
possibly flipped).
* Add lowering for the `firrtl.connect` operation. Since we're currently
lacking the `llhd.con` op, implement this as a `llhd.prb` and
`llhd.drv`. Not *exactly* semantically equivalent, but close enough
given that FIRRTL does not model time anyway.
* update some git and vscode config files
* add HandshakeToFIRRTL files
* Add normal to bundle type conversion
* add handshake to firrtl signature conversion
* add convertMerge and convertReturn function
* update convertmerge code
* add mergeToEntryBlock() function
* remove signature conversion, successfully transform foo.mlir
* foo.mlir support lit test
* add test_inst.mlir testcase
* add module generation for binary ops
* add createBinaryOpModule function
* correctly create new FModule for standard binary operation
* correctly create new FModule for standard binary operation
* correctly connect instance with other operations
* correctly transform test_inst.mlir (binary operation => instance)
* add TODO for 06/29 morning
* support lit test for test_inst.mlir
* support arbitrary binary and unary operations
* add function for checking duplicated FModules
* add remove block structure pass for handshake dialect
* update the combinational logic for binary operation
* update getBundleType function
* clean the existing code
* reorganize code sturcture
* add buildBinaryOp function
* update extractSubfields function
* update buildBinaryOp function
* update getBundleType function
* update createInstOp function
* update code structure, TODO: write buildMergeOp
* update code structure
* update code structure
* support single input merge with instance op; update createInstOp function
* align to upstream repo
* untrack .vscode files
* align with upstream
* align .vscode dir
* align .vscode dir
* Now buildMergeLogic support any number of inputs
* Add buildControlMergeLogic function
* add buildBranchLogic function
* add buildConditionalBranchLogi function
* add buildForkLogic and buildLazyForkLogic function
* add sink, constant operations
* update pass rewrite function, support all (except memory related) elastic component and all binary expressions
* update submodule naming strategy
* update -remove-block-structure pass; -lower-handshake-to-firrtl bugs fix
* add buildJoinLogic function
* bug fixed: instance output connection
* follow clang format
* code cleanup and update testcases
* update testcases
* small bug fixed
* fix CMakeLists for HandshakeToFIRRTL
* update .gitignore
* delete .vscode dir
* fix merge operation logic
* add elastic component test cases
* add elastic component test cases
* add some references
* fix clang formant
* fix some small writing issues
* update test cases
* some small updates
* fix most issues
* emit errors rather than assert
* Merge LLHD project into CIRCT
* Split LLHDOps.td into multiple smaller files
* move LLHDToLLVM init definition and prune includes
* Format tablegen files with 2 space indent, 80 col width; move out trait helper function
* Move implementation logic from LLHDOps.h to cpp file
* Empty lines for breathing space; nicer operation separators
* Move simulator to Dialect/LLHD/Simulator
* move `State.h` and `signal-runtime-wrappers.h` to lib directory
* pass ModuleOp by value
* make getters const, return ModuleOp by value
* Use isa, cast, dyn_cast appropriately
* wrap struct in anon namespace; make helpers static
* [cmake] Fold into LINK_LIBS
* fix for loops
* replace floating point with `divideCeil`
* prune redundant includes
* make llhd-sim helpers static
* remove StandardToLLVM pass registration
* move verilog printer to cpp file, add global function as public API
* Move transformation pass base classes and registration to lib, add file header boilerplate
* Few improvements
* Return diagnostics directly
* isa instead of kindof
* Improve walks
* etc.
* add 'using namespace llvm;' again
* Always pass a location when creating new ops
* Improve cmake files
* remove unnecessary `LLVMSupport` links.
* add `PUBLIC` where missing.
* move LLVMCore under `LINK_COMPONENTS`.
* Add file headers and improve simulator comments
* Some LLHDToLLVM improvements
* Fix walks.
* Use `std::array` instead of `SmallVector` when resize is not needed.
* Fix a potential sefgault by passing an ArrayRef with no data owner.
* Remove some unnecessary steps.
* Remove some unnecessary const strings.
* Add new LowerToLLVMOptions argument
The new argument was added in 10643c9ad85bf072816bd271239281ec50a52e31.
* Add missing file header boilerplate and newline
* Improve for-loop
* use static instead of anonymous namespace for functions
* fit to 80 columns, cast instead of dyn_cast
* Changes for LLVM update
* use llvm format instead of std::stringstream and iomanip
Co-authored-by: rodonisi <simon@rodoni.ch>
Martin Erhart