Commit Graph

3 Commits

Author SHA1 Message Date
Jacques Pienaar 7f1c3399e4
Update to new builder format. (#8785)
Basically did

set(CMAKE_CXX_CLANG_TIDY local/clang-tidy -checks=-*,llvm-use-new-mlir-op-builder -fix)

and then fixed cases where temporary OpBuilders were used (as passed in
by reference now).
2025-07-26 04:55:06 -07:00
Tobias Wölfel f91e77c509
[ImportVerilog] Add support for SVA declarations (#8656)
Support `sequence` and `property` declarations. Slang already handles 
the references and variable ports. Make visiting of `AssertionInstance` 
legal. Those are part of `Expressions` of the `Simple` case. Adapt this 
visitor to handle the varied return types.
2025-07-09 08:40:25 -07:00
Tobias Wölfel b6b1ced097
[ImportVerilog] Add support for concurrent assertions (#8559)
Initial setup for handling SystemVerilog Assertions by adding
AssertionExpr class and integrating LTL dialect. This enables the
foundation for converting SVA expressions to LTL.

Handle concurrent assertion statements by inserting Verif operations
assert and assume operations.
Use `AssertionExpr` to parse the expression.

Add a helper function to convert values to MLIR i1 type for LTL operations.
The function validates that moore::IntType inputs are 1-bit wide and creates
a ConversionOp to handle the conversion from SystemVerilog logic types.

SystemVerilog assertions evaluate expressions to Boolean values where only
'true' results in true, with 'unknown' and 'high impedance' values both
evaluating to false.

This conversion is needed for LTL operations, which only work with i1
types.

Add support for simple assertion expressions. Simple assertions consist 
of an expression, handled by 'Expression.h', and an optional repetition.
Add conversion of the expression type to i1, which is the required input
value of LTL operations.

Add additional timing visitor to add LTL clock operation.
2025-06-19 09:54:21 -07:00