Martin Erhart 175e30d32f [RTG] Rely on textual pass pipeline in Python and CAPI ... The textual pass pipeline has a bit more overhead due to the string parsing, but it reduces the required maintenance as we don't have to write CAPI and Python bindings for all the pass options.		2025-07-29 17:48:13 +01:00
..
Dialect	[RTG] Use tablegen generated pass registration	2025-07-29 17:48:13 +01:00
Firtool	[firrtl] Move LowerLayers after LowerXMR (#8405)	2025-04-24 11:02:55 -04:00
Support	[HW][AIG] Add InstancePath CAPI and use native structures for AIG longest path analysis (#8760)	2025-07-22 11:30:43 -07:00
Conversion.h	[CAPI] disambiguate mlirRegisterConversionPasses (#8072)	2025-01-13 16:40:28 -05:00
ExportFIRRTL.h	[ExportFIRRTL] Implement C API	2023-06-13 23:46:35 +08:00
ExportVerilog.h	[Python] Expose exportSplitVerilog API to Python.	2021-11-09 13:28:54 -07:00
Synthesis.h	[circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure (#8681)	2025-07-10 16:16:11 -07:00
Transforms.h	[CAPI] disambiguate mlirRegisterConversionPasses (#8072)	2025-01-13 16:40:28 -05:00