Martin Erhart 175e30d32f [RTG] Rely on textual pass pipeline in Python and CAPI ... The textual pass pipeline has a bit more overhead due to the string parsing, but it reduces the required maintenance as we don't have to write CAPI and Python bindings for all the pass options.		2025-07-29 17:48:13 +01:00
..
Bindings	[RTG] Rely on textual pass pipeline in Python and CAPI	2025-07-29 17:48:13 +01:00
Dialect	[ESI] Make RAM delarations' addresses unsigned (#8658)	2025-07-07 12:43:12 -07:00
EmitVerilog	[FIRRTL] Remove test usage of '<=' connect, NFC	2024-10-25 16:59:12 -04:00
Target/ExportSystemC	[LLVM] bump to 9deb08a and integrate upstream SMT C APIs (#8424)	2025-04-17 15:26:22 -04:00
arcilator/JIT	[Arcilator] Don't try to run JIT if only part of the pipeline is run (#8575)	2025-06-18 10:14:24 +01:00
circt-bmc	[circt-bmc] Support `seq.firreg` with sync reset (#8698)	2025-07-21 17:34:37 +01:00
circt-lec	[circt-lec] Adding support for the datapath dialect (#8721)	2025-07-18 09:21:58 +01:00
circt-rtl-sim	[ESI] [Integration tests] [Tests] Switch from 'rstn' to 'rst' (#3618)	2022-07-28 10:55:58 -07:00
circt-synth	[HW][HWAggregateToComb] Add support for hw.array_inject operation in HWAggregateToComb pass (#8788)	2025-07-28 11:34:15 -07:00
circt-test	[verif] add booth contract example (#8319)	2025-03-21 14:51:58 -07:00
handshake-runner	[Handshake] `StandardToHandshake` -> `CFToHandshake` (#5938)	2023-08-25 09:24:26 +02:00
CMakeLists.txt	Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. (#8225)	2025-02-13 14:32:11 -07:00
lit.cfg.py	[AIG] Add AIGER runner passes for external logic solver integration (#8592)	2025-06-23 15:16:59 -07:00
lit.site.cfg.py.in	[circt-test] fix SymbiYosys integration test (#7886)	2025-03-05 11:10:59 -08:00