mirror of https://github.com/llvm/circt.git
8c1865c5a9
Using signless ints as the address was just wrong. It was probably done to avoid incomplete lowerings, which have been addressed. Changes RAM declaration addresses to use unsigned integer types throughout the ESI dialect and its tests, updating both the code generator and expected outputs. - Switch address ports to unsigned (uiN) in MLIR tests and service definitions. - Update service port generation and SystemVerilog memory instantiation to use unsigned address types, inserting bitcasts to signless for indexing. - Adjust PyCDE front end and software integration tests to use UInt addressing. |
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| .. | ||
| add-ids.mlir | ||
| call.mlir | ||
| canonicalization.mlir | ||
| compose-buffers.mlir | ||
| errors-lock-functions.mlir | ||
| errors-memory.mlir | ||
| errors.mlir | ||
| func.mlir | ||
| insert-buffer-all.mlir | ||
| insert-buffer-cycles.mlir | ||
| insert-buffer-invalid.mlir | ||
| join.mlir | ||
| legalize-memrefs.mlir | ||
| lower-extmem-esi.mlir | ||
| lower-extmem.mlir | ||
| materialize.mlir | ||
| remove_buffers.mlir | ||
| split-merge.mlir | ||
| sync.mlir | ||
| test-dematerialize.mlir | ||
| test-lock-functions.mlir | ||
| tuple-ops.mlir | ||