Prithayan Barua 2beb8e783f [OM] Deprecate the OM Map and Tuple (#8606) ... Remove the support for OM Map and Tuple. All the dependence on them have been removed. --------- Co-authored-by: Mike Urbach <mikeurbach@gmail.com>		2025-07-14 19:57:59 -07:00
..
Bindings	[OM] Deprecate the OM Map and Tuple (#8606)	2025-07-14 19:57:59 -07:00
Dialect	[ESI] Make RAM delarations' addresses unsigned (#8658)	2025-07-07 12:43:12 -07:00
EmitVerilog	[FIRRTL] Remove test usage of '<=' connect, NFC	2024-10-25 16:59:12 -04:00
Target/ExportSystemC	[LLVM] bump to 9deb08a and integrate upstream SMT C APIs (#8424)	2025-04-17 15:26:22 -04:00
arcilator/JIT	[Arcilator] Don't try to run JIT if only part of the pipeline is run (#8575)	2025-06-18 10:14:24 +01:00
circt-bmc	[circt-bmc] Support registers with reset signals (#8622)	2025-07-02 16:52:51 +01:00
circt-lec	[HWToSMT] ArrayCreateOp and ArrayGetOp support (#7666)	2024-11-29 11:36:44 +00:00
circt-rtl-sim	[ESI] [Integration tests] [Tests] Switch from 'rstn' to 'rst' (#3618)	2022-07-28 10:55:58 -07:00
circt-synth	[AIG] Add AIGER runner passes for external logic solver integration (#8592)	2025-06-23 15:16:59 -07:00
circt-test	[verif] add booth contract example (#8319)	2025-03-21 14:51:58 -07:00
handshake-runner	[Handshake] `StandardToHandshake` -> `CFToHandshake` (#5938)	2023-08-25 09:24:26 +02:00
CMakeLists.txt	Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. (#8225)	2025-02-13 14:32:11 -07:00
lit.cfg.py	[AIG] Add AIGER runner passes for external logic solver integration (#8592)	2025-06-23 15:16:59 -07:00
lit.site.cfg.py.in	[circt-test] fix SymbiYosys integration test (#7886)	2025-03-05 11:10:59 -08:00