mirror of https://github.com/llvm/circt.git
42 lines
1.5 KiB
MLIR
42 lines
1.5 KiB
MLIR
// REQUIRES: iverilog,cocotb
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// Test 1: default lowering
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// RUN: circt-opt %s -pipeline-explicit-regs -lower-pipeline-to-hw -lower-seq-to-sv -sv-trace-iverilog -export-verilog \
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// RUN: -o %t.mlir > %t.sv
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// RUN: circt-cocotb-driver.py --objdir=%T --topLevel=simple \
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// RUN: --pythonModule=simple --pythonFolder="%S,%S/.." %t.sv 2>&1 | FileCheck %s
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// Test 2: Clock-gate implementation
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// RUN: circt-opt %s -pipeline-explicit-regs -lower-pipeline-to-hw="clock-gate-regs" -lower-seq-to-sv -sv-trace-iverilog -export-verilog \
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// RUN: -o %t.mlir > %t_cg.sv
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// RUN: circt-cocotb-driver.py --objdir=%T --topLevel=simple \
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// RUN: --pythonModule=simple --pythonFolder="%S,%S/.." %t_cg.sv 2>&1 | FileCheck %s
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// CHECK: ** TEST
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// CHECK: ** TESTS=[[N:.*]] PASS=[[N]] FAIL=0 SKIP=0
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hw.module @simple(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clock : !seq.clock, in %reset : i1, out out: i32, out done : i1) {
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%out, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clock) reset(%reset) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%add0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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%add0_bb1 = pipeline.src %add0 : i32
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%a0_bb1 = pipeline.src %a0 : i32
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%add1 = comb.add %add0_bb1, %a0_bb1 : i32
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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%add0_bb2 = pipeline.src %add0 : i32
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%add1_bb2 = pipeline.src %add1 : i32
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%add2 = comb.add %add1_bb2, %add0_bb2 : i32
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pipeline.return %add2 : i32
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}
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hw.output %out, %done : i32, i1
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}
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