mirror of https://github.com/llvm/circt.git
256 lines
6.7 KiB
MLIR
256 lines
6.7 KiB
MLIR
// RUN: circt-opt %s --split-input-file --verify-diagnostics
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// expected-error @below {{types of the yielded values of both regions must match}}
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verif.lec first {
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^bb0(%arg0: i32):
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verif.yield %arg0 : i32
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} second {
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^bb0(%arg0: i32):
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verif.yield
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}
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// -----
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// expected-error @below {{block argument types of both regions must match}}
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verif.lec first {
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^bb0(%arg0: i32, %arg1: i32):
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verif.yield %arg0 : i32
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} second {
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^bb0(%arg0: i32):
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{types of the yielded values of both regions must match}}
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verif.refines first {
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^bb0(%arg0: i32):
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verif.yield %arg0 : i32
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} second {
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^bb0(%arg0: i32):
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verif.yield
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}
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// -----
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// expected-error @below {{block argument types of both regions must match}}
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verif.refines first {
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^bb0(%arg0: i32, %arg1: i32):
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verif.yield %arg0 : i32
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} second {
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^bb0(%arg0: i32):
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{init region must have no arguments}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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^bb0(%clk: !seq.clock):
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} loop {
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^bb0(%clk: !seq.clock):
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} circuit {
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^bb0(%clk: !seq.clock, %arg0: i32):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{init and loop regions must yield the same types of values}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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verif.yield %toClk, %toClk : !seq.clock, !seq.clock
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} loop {
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^bb0(%clk1: !seq.clock, %clk2: !seq.clock, %arg0: i32):
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verif.yield %clk1, %arg0 : !seq.clock, i32
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} circuit {
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^bb0(%clk1: !seq.clock, %clk2: !seq.clock, %arg0: i32):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{init and loop regions must yield the same types of values}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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%c1_i2 = hw.constant 2 : i2
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verif.yield %toClk, %c1_i2 : !seq.clock, i2
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} loop {
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^bb0(%clk1: !seq.clock, %arg0: i32, %state: i1):
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verif.yield %clk1, %state : !seq.clock, i1
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} circuit {
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^bb0(%clk1: !seq.clock, %arg0: i32, %state: i1):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{loop region arguments must match the types of the values yielded by the init and loop regions}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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%c1_i2 = hw.constant 2 : i2
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verif.yield %toClk, %c1_i2 : !seq.clock, i2
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} loop {
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^bb0(%clk1: !seq.clock, %state: i2, %arg0: i32):
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verif.yield %clk1, %state : !seq.clock, i2
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} circuit {
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^bb0(%clk1: !seq.clock, %arg0: i32, %state: i1):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{init and loop regions must yield at least as many clock values as there are clock arguments to the circuit region}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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verif.yield %toClk: !seq.clock
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} loop {
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^bb0(%clk1: !seq.clock):
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verif.yield %clk1 : !seq.clock
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} circuit {
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^bb0(%clk1: !seq.clock, %clk2: !seq.clock, %arg0: i32):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{init and loop regions must yield as many clock values as there are clock arguments in the circuit region before any other values}}
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verif.bmc bound 10 num_regs 0 initial_values [] init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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verif.yield %toClk, %clkInit, %toClk: !seq.clock, i1, !seq.clock
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} loop {
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^bb0(%clk1: !seq.clock, %state: i1, %clk2: !seq.clock):
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verif.yield %clk1, %state, %clk2 : !seq.clock, i1, !seq.clock
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} circuit {
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^bb0(%clk1: !seq.clock, %clk2: !seq.clock, %arg0: i32):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{number of initial values must match the number of registers}}
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verif.bmc bound 10 num_regs 0 initial_values [unit] attributes {verif.some_attr} init {
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} loop {
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} circuit {
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^bb0(%arg0: i32):
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%false = hw.constant false
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// Arbitrary assertion so op verifies
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verif.assert %false : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{number of initial values must match the number of registers}}
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verif.bmc bound 10 num_regs 1 initial_values [] attributes {verif.some_attr} init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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verif.yield %toClk : !seq.clock
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} loop {
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^bb0(%clk1: !seq.clock):
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verif.yield %clk1 : !seq.clock
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} circuit {
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^bb0(%clk: !seq.clock, %arg0: i32):
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%false = hw.constant false
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// Arbitrary assertion so op verifies
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verif.assert %false : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{initial values must be integer or unit attributes}}
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verif.bmc bound 10 num_regs 1 initial_values ["foo"] attributes {verif.some_attr} init {
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%clkInit = hw.constant false
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%toClk = seq.to_clock %clkInit
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verif.yield %toClk : !seq.clock
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} loop {
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^bb0(%clk1: !seq.clock):
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verif.yield %clk1 : !seq.clock
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} circuit {
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^bb0(%clk: !seq.clock, %arg0: i32):
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%false = hw.constant false
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// Arbitrary assertion so op verifies
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verif.assert %false : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{num_regs is non-zero, but the circuit region has no clock inputs to clock the registers}}
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verif.bmc bound 10 num_regs 1 initial_values [unit] attributes {verif.some_attr} init {
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} loop {
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} circuit {
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^bb0(%arg0: i32):
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%true = hw.constant true
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verif.assert %true : i1
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verif.yield %arg0 : i32
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}
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// -----
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// expected-error @below {{op must have two block arguments}}
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verif.simulation @foo {} {
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^bb0(%arg0: !seq.clock):
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%true = hw.constant true
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verif.yield %true, %true : i1, i1
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}
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// -----
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// expected-error @below {{op block argument #0 must be of type `!seq.clock`}}
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verif.simulation @foo {} {
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^bb0(%arg0: i1, %arg1: i1):
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verif.yield %arg0, %arg1 : i1, i1
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}
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// -----
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// expected-error @below {{op block argument #1 must be of type `i1`}}
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verif.simulation @foo {} {
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^bb0(%arg0: !seq.clock, %arg1: i42):
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%true = hw.constant true
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verif.yield %true, %true : i1, i1
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}
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// -----
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verif.simulation @foo {} {
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^bb0(%arg0: !seq.clock, %arg1: i1):
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// expected-error @below {{op must have two operands}}
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verif.yield
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}
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// -----
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verif.simulation @foo {} {
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^bb0(%arg0: !seq.clock, %arg1: i1):
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// expected-error @below {{op operand #0 must be of type `i1`}}
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verif.yield %arg0, %arg1 : !seq.clock, i1
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}
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// -----
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verif.simulation @foo {} {
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^bb0(%arg0: !seq.clock, %arg1: i1):
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// expected-error @below {{op operand #1 must be of type `i1`}}
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verif.yield %arg1, %arg0 : i1, !seq.clock
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}
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