mirror of https://github.com/llvm/circt.git
40 lines
1.4 KiB
MLIR
40 lines
1.4 KiB
MLIR
// RUN: arcilator %s --run --jit-entry=main | FileCheck %s
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// REQUIRES: arcilator-jit
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// CHECK: c = 0
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// CHECK-NEXT: c = 5
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sim.func.dpi @dpi(in %a : i32, in %b : i32, out c : i32) attributes {verilogName = "adder_func"}
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func.func @adder_func(%arg0: i32, %arg1: i32, %arg2: !llvm.ptr) {
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%0 = arith.addi %arg0, %arg1 : i32
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llvm.store %0, %arg2 : i32, !llvm.ptr
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return
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}
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hw.module @adder(in %clock : i1, in %a : i32, in %b : i32, out c : i32) {
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%seq_clk = seq.to_clock %clock
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%0 = sim.func.dpi.call @dpi(%a, %b) clock %seq_clk : (i32, i32) -> i32
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hw.output %0 : i32
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}
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func.func @main() {
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%c2_i32 = arith.constant 2 : i32
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%c3_i32 = arith.constant 3 : i32
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%one = arith.constant 1 : i1
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%zero = arith.constant 0 : i1
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arc.sim.instantiate @adder as %arg0 {
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arc.sim.set_input %arg0, "a" = %c2_i32 : i32, !arc.sim.instance<@adder>
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arc.sim.set_input %arg0, "b" = %c3_i32 : i32, !arc.sim.instance<@adder>
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arc.sim.set_input %arg0, "clock" = %one : i1, !arc.sim.instance<@adder>
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arc.sim.step %arg0 : !arc.sim.instance<@adder>
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arc.sim.set_input %arg0, "clock" = %zero : i1, !arc.sim.instance<@adder>
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%0 = arc.sim.get_port %arg0, "c" : i32, !arc.sim.instance<@adder>
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arc.sim.emit "c", %0 : i32
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arc.sim.step %arg0 : !arc.sim.instance<@adder>
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arc.sim.set_input %arg0, "clock" = %one : i1, !arc.sim.instance<@adder>
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%2 = arc.sim.get_port %arg0, "c" : i32, !arc.sim.instance<@adder>
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arc.sim.emit "c", %2 : i32
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}
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return
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}
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