Prithayan Barua dde9f4bc96 [Seq] Canonicalize firreg with a preset (#7350) ... The canonicalization was ignoring any registers with a preset, this commit fixes that. Add fold and canonicalization patterns for registers with a preset.		2024-07-19 09:23:33 -07:00
..
Analysis	Move 'using namespace' out of headers. (#6844)	2024-03-18 16:57:03 +01:00
Bindings	[PyCDE][ESI] Manifest: add record about client (#7299)	2024-07-10 06:59:43 -07:00
CAPI	[HW][CAPI][NFC] Fix cast warning.	2024-07-10 15:58:03 -05:00
Conversion	[MooreToCore] Support NegOp lowering (#7344)	2024-07-19 00:42:12 +01:00
Dialect	[Seq] Canonicalize firreg with a preset (#7350)	2024-07-19 09:23:33 -07:00
Firtool	Revert "[FIRRTL] Enable Wire Elimination (#7073)" (#7311)	2024-07-12 08:51:52 -07:00
Reduce	Bump LLVM (#7223)	2024-06-26 13:19:37 -07:00
Scheduling	[Calyx][OM][Pipeline] Use free variants of isa/cast/dyn_cast	2024-04-28 16:53:58 +02:00
Support	Bump LLVM (#7223)	2024-06-26 13:19:37 -07:00
Target	[HGLDD] Quiet unused warnings for operator<< in release build.	2024-05-30 12:06:22 -05:00
Tools	[circt-bmc] Add ExternalizeRegisters Pass (#7285)	2024-07-16 19:34:12 +01:00
Transforms	[NFCI][Transforms] Refactor TableGen Pass includes (#7173)	2024-06-14 19:13:15 +02:00
CMakeLists.txt	[circt-lec] Port to SMT dialect based compiler pipeline (#6908)	2024-04-21 08:06:39 +02:00