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AffineToLoopSchedule
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[LoopSchedule] Move PipelineWhile and Related Ops from Pipeline to LoopSchedule (#4947)
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2023-04-18 11:56:07 -04:00 |
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ArcToLLVM
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[Arc] Add support for struct and array states (#6508)
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2023-12-11 14:22:25 -08:00 |
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CFToHandshake
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[Handshake] `StandardToHandshake` -> `CFToHandshake` (#5938)
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2023-08-25 09:24:26 +02:00 |
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CalyxToFSM
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[Seq] Switch all seq ops to use seq.clock (#6139)
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2023-09-18 16:38:32 +03:00 |
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CalyxToHW
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Add emission for calyx std_signext (#6285)
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2023-10-12 12:17:44 -04:00 |
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CombToArith
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[CombToArith] Fix coarsening of division by zero UB (#6945)
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2024-05-06 15:59:36 +02:00 |
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CombToSMT
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[CombToSMT] Register dependency on func (#7098)
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2024-05-28 21:46:54 +02:00 |
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ConvertToArcs
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[Arc] StateOp: latency instead of lat in assembly format (#6562)
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2024-01-12 07:54:39 +01:00 |
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DCToHW
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[DC] Add merge lowering (#6943)
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2024-05-07 10:21:25 +02:00 |
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ExportChiselInterface
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[ExportChiselInterface] Support probe types (#5497)
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2023-06-30 09:22:46 -06:00 |
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ExportVerilog
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[SV] Add UnpackedArrayCreateOp (#7303)
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2024-07-18 19:53:12 +09:00 |
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FIRRTLToHW
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[FIRRTL] Error when seeing inner symbols on zero-width wires and nodes in LowerToHW
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2024-07-01 10:40:44 -05:00 |
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FSMToSV
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[FSM][Emit] Convert the FSMToSV pass to use `emit` ops (#6828)
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2024-03-19 19:30:02 +02:00 |
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HWArithToHW
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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HWToBTOR2
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[FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150)
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2024-06-20 11:24:37 -07:00 |
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HWToLLHD
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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HWToLLVM
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Bump LLVM (#7223)
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2024-06-26 13:19:37 -07:00 |
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HWToSMT
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[circt-lec] Port to SMT dialect based compiler pipeline (#6908)
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2024-04-21 08:06:39 +02:00 |
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HWToSV
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[NFC][HW] Fix parsing of nullary hw.triggered ops (#7291)
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2024-07-09 17:51:03 +02:00 |
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HWToSystemC
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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HandshakeToDC
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[Handshake] Add control_merge deconstruction pattern (#6934)
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2024-05-07 11:08:04 +02:00 |
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HandshakeToHW
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[Seq] Add optional power-on value to `compreg` ops (#6255)
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2023-10-09 11:11:15 +02:00 |
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ImportVerilog
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[Moore] Make ReadOp infer its result type
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2024-07-18 15:15:16 -07:00 |
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LLHDToLLVM
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Bump LLVM (#7223)
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2024-06-26 13:19:37 -07:00 |
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LTLToCore
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[FIRRTL][Verif][LTL] Replace `ltl.disable` with an enable folded into `verif.assert` (#7150)
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2024-06-20 11:24:37 -07:00 |
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LoopScheduleToCalyx
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[SCF-To-Calyx] Fixes Bugs (#5573)
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2023-07-13 18:25:05 -04:00 |
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MooreToCore
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[MooreToCore] Support NegOp lowering (#7344)
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2024-07-19 00:42:12 +01:00 |
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PipelineToHW
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[PipelineToHW] Add optional power-on values to control registers (#6269)
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2023-10-10 11:10:16 +02:00 |
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SCFToCalyx
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[Calyx] Switch sequential memories to be true single port memories (#6765)
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2024-02-29 11:15:34 -05:00 |
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SMTToZ3LLVM
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[SMT] Add quantifier support to LLVM lowering (#6973)
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2024-05-02 10:09:14 +02:00 |
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SeqToSV
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[SeqToSV] Fix the ordering of the memory/register random init fragments (#6883)
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2024-04-01 18:56:45 +03:00 |
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SimToSV
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[ExportVerilog] Add "context" to imported DPI functions (#7333)
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2024-07-18 03:58:47 +09:00 |
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VerifToSMT
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Bump LLVM (#7223)
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2024-06-26 13:19:37 -07:00 |
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VerifToSV
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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