circt/tools
mingzheTerapines b7afc536db
[ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type (#7158)
For the new concept of Moore dialect, some operations will be defined as memory-related operations. Modeling memref Dialect and LLVM dialect, the operation relationship is as follows:

ReadOp and blockingAssignOp are related to loadOp and storeOp.
VariableOp is related to allocaOp.
However, the operations mentioned below are for basic types. This PR will support nested types in the following way:

VariableOp with nested types is still related to allocaOp (will be replaced with structCreateOp and UnionCreateOp).
structExtractRefOp is related to storeOp.
structExtractOp is related to loadOp.
To implement this:

Since these operations will be lowered to the hw dialect, the design largely refers to the hw dialect.

Add the trait DestructurableAllocationOpInterface for VariableOp.

Add the trait DestructurableAccessorOpInterface for structExtractOp and structExtractRefOp.

Implement the DestructurableTypeInterface for structLikeType and the reftype of structLikeType.

For local variables:

Use the SROA (Scalar Replacement of Aggregates) Pass to destructure all nested-type variables into basic-type variables.
Use the Mem2Reg (Memory to Register) Pass to replace variables imported by SROA with constants.
For global/module-level variables:

When importing Verilog, use structInjectOp rather than blockingAssignOp, because structExtractRefOp has the Destructurable trait, but global variables should not be destructured.
structInjectOp means creating a new struct with new values and other old values.
Use the canonicalizer Pass to fold duplicate injecting same field operations.
Use the canonicalizer Pass to explicitly show new struct creation.
Use the canonicalizer Pass to send source values directly and remove structExtractOp.
Also, remove some unnecessary spaces in other code.

What's more:

Verify that the input of nested-type-related operations should match the field type defined.
To do:

Update the use of struct SSA values referring to the latest structInjectOp SSA values.
Design the method for union types.
Add and support the dbg dialect to keep local variables visible after SROA & Mem2Reg.

Co-authored-by: Théo Degioanni <degiotheo@gmail.com>
Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>
2024-07-18 10:56:37 +08:00
..
arcilator [NFC] tools: remove unused iostream header. 2024-05-17 13:15:39 -05:00
circt-as [CMake] Implement add_circt_tool() (#5821) 2023-08-10 18:37:45 -05:00
circt-cocotb-driver Move cocotb driver to separate tool (#5279) 2023-05-30 09:48:47 +02:00
circt-dis [CMake] Implement add_circt_tool() (#5821) 2023-08-10 18:37:45 -05:00
circt-lec [circt-lec] Port to SMT dialect based compiler pipeline (#6908) 2024-04-21 08:06:39 +02:00
circt-lsp-server [CMake] Implement add_circt_tool() (#5821) 2023-08-10 18:37:45 -05:00
circt-opt [ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type (#7158) 2024-07-18 10:56:37 +08:00
circt-reduce [CMake] Implement add_circt_tool() (#5821) 2023-08-10 18:37:45 -05:00
circt-rtl-sim [RTL sim] Add option to run verilator with valgrind 2023-12-11 23:59:16 +00:00
circt-translate [circt-translate] Make ImportVerilog registration conditional 2024-02-21 12:12:23 -08:00
circt-verilog [ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type (#7158) 2024-07-18 10:56:37 +08:00
firtool [firtool] Support layer specialization 2024-06-14 15:48:53 -07:00
handshake-runner [Handshake] Use free variants of isa/cast/dyn_cast 2024-04-28 15:57:40 +02:00
hlstool Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
ibistool Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
llhd-sim Bump LLVM (#7223) 2024-06-26 13:19:37 -07:00
om-linker [NFC][SV] Remove unnecessary SV dependency on Verif (#7249) 2024-06-28 14:48:44 +01:00
py-split-input-file [PyCDE] Add .py ext to py-split-input-file to make Windows happy 2022-06-17 14:13:46 +02:00
CMakeLists.txt [ESI] Move entirely over to the runtime for testing (#6764) 2024-02-28 22:29:29 -08:00