From 4fb8a3fdc664ce2df51e7a19a0bd24e2fb04f346 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Tue, 10 Sep 2024 11:03:31 +0700 Subject: [PATCH] Add Adafruit qtpy ch32v203 board (#136) * add adafruit qtpy ch32v203g6 board * use 224KB for qtpy v203, implement pre_iint() to enable enhanced read mode --- boards.txt | 16 ++ tools/makeboards.py | 1 + .../CH32V203G6_ADAFRUIT_QTPY/CMakeLists.txt | 30 +++ .../CH32V203G6_ADAFRUIT_QTPY/PeripheralPins.c | 215 ++++++++++++++++++ .../CH32V203G6_ADAFRUIT_QTPY/PinNamesVar.h | 53 +++++ .../variant_CH32V203G6_ADAFRUIT_QTPY.cpp | 56 +++++ .../variant_CH32V203G6_ADAFRUIT_QTPY.h | 170 ++++++++++++++ 7 files changed, 541 insertions(+) create mode 100644 variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/CMakeLists.txt create mode 100644 variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PeripheralPins.c create mode 100644 variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PinNamesVar.h create mode 100644 variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.cpp create mode 100644 variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.h diff --git a/boards.txt b/boards.txt index 73d4c4c..32fbe00 100644 --- a/boards.txt +++ b/boards.txt @@ -524,6 +524,22 @@ CH32V20x_EVT.menu.pnum.CH32V203C6.build.math_lib_gcc=-lm CH32V20x_EVT.menu.pnum.CH32V203C6.build.IQ_math_RV32= CH32V20x_EVT.menu.pnum.CH32V203C6.build.ch_extra_lib=-lprintf +#Adafruit QTPy CH32V203G6 Board +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY=Adafruit QTPy CH32V203G6 +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.node=NODE_V203G6_ADAFRUIT_QTPY +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.upload.maximum_size=229376 +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.upload.maximum_data_size=10240 +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.mcu=QingKe-V4B +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.board=CH32V203G6_ADAFRUIT_QTPY +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.series=CH32V20x +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.variant=CH32V20x/CH32V203G6_ADAFRUIT_QTPY +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.chip=CH32V203 +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.march=rv32imacxw +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.mabi=ilp32 +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.math_lib_gcc=-lm +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.IQ_math_RV32= +CH32V20x_EVT.menu.pnum.CH32V203G6_ADAFRUIT_QTPY.build.ch_extra_lib=-lprintf + # USB support CH32V20x_EVT.menu.usb.none=None diff --git a/tools/makeboards.py b/tools/makeboards.py index 40c0abd..71a526e 100644 --- a/tools/makeboards.py +++ b/tools/makeboards.py @@ -80,6 +80,7 @@ board_list = { 'CH32V203G6': {'name': 'CH32V203G6 EVT', 'maximum_size': 32768, 'maximum_data_size': 10240, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'}, 'CH32V203C8': {'name': 'CH32V203C8', 'maximum_size': 65536, 'maximum_data_size': 20480, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'}, 'CH32V203C6': {'name': 'CH32V203C6', 'maximum_size': 32768, 'maximum_data_size': 10240, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'}, + 'CH32V203G6_ADAFRUIT_QTPY': {'name': 'Adafruit QTPy CH32V203G6', 'maximum_size': 229376, 'maximum_data_size': 10240, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'}, } }, 'CH32V30x': { diff --git a/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/CMakeLists.txt b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/CMakeLists.txt new file mode 100644 index 0000000..5738501 --- /dev/null +++ b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/CMakeLists.txt @@ -0,0 +1,30 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + PeripheralPins.c + variant_CH32V203G6_ADAFRUIT_QTPY.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PeripheralPins.c b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PeripheralPins.c new file mode 100644 index 0000000..28b60f2 --- /dev/null +++ b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PeripheralPins.c @@ -0,0 +1,215 @@ +/** + ******************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * All rights reserved. + * + * This software component is licensed by WCH under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** +#ifdef ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC2_IN0 + {PA_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC2_IN1 + {PA_2, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC2_IN2 + {PA_3, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC2_IN3 + {PA_4, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC1_IN4 + {PA_4_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC2_IN4 + {PA_5, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC1_IN5 + {PA_5_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC2_IN5 + {PA_6, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC1_IN6 + {PA_6_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC2_IN6 + {PA_7, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC1_IN7 + {PA_7_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC2_IN7 + {PB_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC1_IN8 + {PB_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC2_IN8 + {PB_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC1_IN9 + {PB_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC2_IN9 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + + + +//*** I2C *** +#ifdef I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)}, + {PB_9, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)}, + {NC, NP, 0} +}; +#endif + +#ifdef I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)}, + {PB_8, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)}, + {NC, NP, 0} +}; +#endif + +//*** TIM *** +#ifdef TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1 + {PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2 + {PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3 + {PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4 + + {PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1 + {PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2 + {PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3 + {PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4 + + {PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1 + {PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2 + {PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3 + {PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4 + + {PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1 + {PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2 + {PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3 + {PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4 + + {PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N + {PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N + {PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N + {NC, NP, 0} +}; +#endif + +//*** UART *** +#ifdef UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_9, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PB_6, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_Remap_USART1_ENABLE)}, + {PA_2, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PB_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PC_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART3_ENABLE)}, + {PB_0, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PA_5, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART4_ENABLE)}, + {NC, NP, 0} +}; +#endif + +#ifdef UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_10, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PB_7, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_Remap_USART1_ENABLE)}, + {PA_3, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PB_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PC_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART3_ENABLE)}, + {PB_1, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PB_5, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART4_ENABLE)}, + {NC, NP, 0} +}; +#endif + +#ifdef UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PA_1, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PB_14, USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {PB_4, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_11, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PA_0, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PB_13, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {PB_3, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + + +//*** SPI *** +#ifdef SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_FLOAT, 0, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + +#ifdef SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)}, + {NC, NP, 0} +}; +#endif + +//*** CAN *** +#ifdef CAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, + {PB_8, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_CAN1_2)}, + {NC, NP, 0} +}; +#endif + +#ifdef CAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)}, + {PB_9, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_CAN1_2)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + + + +//*** USB *** +#ifdef USB_MODULE_ENABLED +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DM + {PA_12, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** No SD *** + + diff --git a/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PinNamesVar.h b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PinNamesVar.h new file mode 100644 index 0000000..2b0fb9d --- /dev/null +++ b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/PinNamesVar.h @@ -0,0 +1,53 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_2_ALT1 = PA_2 | ALT1, +PA_3_ALT1 = PA_3 | ALT1, +PA_4_ALT1 = PA_4 | ALT1, +PA_5_ALT1 = PA_5 | ALT1, +PA_6_ALT1 = PA_6 | ALT1, +PA_7_ALT1 = PA_7 | ALT1, +PA_8_ALT1 = PA_8 | ALT1, +PA_9_ALT1 = PA_9 | ALT1, +PA_10_ALT1 = PA_10 | ALT1, +PA_11_ALT1 = PA_11 | ALT1, +PA_15_ALT1 = PA_15 | ALT1, +PB_0_ALT1 = PB_0 | ALT1, +PB_0_ALT2 = PB_0 | ALT2, +PB_1_ALT1 = PB_1 | ALT1, +PB_1_ALT2 = PB_1 | ALT2, +PB_3_ALT1 = PB_3 | ALT1, +PB_10_ALT1 = PB_10 | ALT1, +PB_11_ALT1 = PB_11 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = NC, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = NC, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = NC, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = NC, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = NC, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = NC, +#endif + +/* USB */ +#ifdef USBCON + USB_DM = PA_11, + USB_DP = PA_12, +#endif diff --git a/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.cpp b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.cpp new file mode 100644 index 0000000..403f43f --- /dev/null +++ b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.cpp @@ -0,0 +1,56 @@ +/** + ******************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * All rights reserved. + * + * This software component is licensed by WCH under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#include "pins_arduino.h" +#include "hw_config.h" + +// Digital PinName array +const PinName digitalPin[] = { + PB_1, // D0/A0 + PB_0, // D1/A1 + PA_1, // D2/A2 + PA_0, // D3/A3 + PA_2, // D4/TX + PA_3, // D5/RX + PA_4, // D6/Neopixel + PA_5, // D7/SCK + PA_6, // D8/MISO + PA_7, // D9/MOSI + PB_6, // D10/SCL + PB_7, // D11/SDA + PB_8, // D12/BOOT0 Button +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PB1 + 1, // A1, PB0 + 2, // A2, PA1 + 3, // A3, PA0 +}; + +extern "C" { + +void pre_init(void) { + // Enable Flash enhance read mode for full 224KB + FLASH->KEYR = 0x45670123; // FLASH_Unlock_Fast(); + FLASH->KEYR = 0xCDEF89AB; + + FLASH->CTLR |= (1 << 24); // Enhanced Read Mode + + FLASH->CTLR |= (1 << 15); // FLASH_Lock_Fast(); + + hw_config_init(); +} + +} \ No newline at end of file diff --git a/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.h b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.h new file mode 100644 index 0000000..3313b10 --- /dev/null +++ b/variants/CH32V20x/CH32V203G6_ADAFRUIT_QTPY/variant_CH32V203G6_ADAFRUIT_QTPY.h @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * All rights reserved. + * + * This software component is licensed by WCH under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/* ENABLE Peripherals */ +#define ADC_MODULE_ENABLED +#define UART_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define TIM_MODULE_ENABLED + +/* CH32V203G6 Pins */ +#define PA0 3 +#define PA1 2 +#define PA2 4 +#define PA3 5 +#define PA4 6 +#define PA5 7 +#define PA6 8 +#define PA7 9 +#define PA8 PNUM_NOT_DEFINED +#define PA9 PNUM_NOT_DEFINED +#define PA10 PNUM_NOT_DEFINED +#define PA11 PNUM_NOT_DEFINED +#define PA12 PNUM_NOT_DEFINED +#define PA13 PNUM_NOT_DEFINED +#define PA14 PNUM_NOT_DEFINED +#define PA15 PNUM_NOT_DEFINED +#define PB0 PIN_A1 +#define PB1 PIN_A0 +#define PB2 PNUM_NOT_DEFINED +#define PB3 PNUM_NOT_DEFINED +#define PB4 PNUM_NOT_DEFINED +#define PB5 PNUM_NOT_DEFINED +#define PB6 10 +#define PB7 11 +#define PB8 12 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA8_ALT1 (PA8 | ALT1) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) + +#define NUM_DIGITAL_PINS 13 +#define NUM_ANALOG_INPUTS 4 +// #define ADC_CTLR_ADCAL +#define ADC_RESOLUTION 12 + + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PB8 +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif + +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM3 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM2 +#endif + + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 +#endif +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif + +