forked from OSchip/llvm-project
[X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsBitMask. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available. llvm-svn: 286039
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@ -7484,6 +7484,7 @@ static SDValue lowerVectorShuffleWithUNPCK(const SDLoc &DL, MVT VT,
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/// one of the inputs being zeroable.
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static SDValue lowerVectorShuffleAsBitMask(const SDLoc &DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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const SmallBitVector &Zeroable,
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SelectionDAG &DAG) {
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MVT EltVT = VT.getVectorElementType();
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int NumEltBits = EltVT.getSizeInBits();
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@ -7496,7 +7497,6 @@ static SDValue lowerVectorShuffleAsBitMask(const SDLoc &DL, MVT VT, SDValue V1,
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AllOnes = DAG.getBitcast(EltVT, AllOnes);
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}
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SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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SDValue V;
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for (int i = 0, Size = Mask.size(); i < Size; ++i) {
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if (Zeroable[i])
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@ -7673,7 +7673,8 @@ static SDValue lowerVectorShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1,
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"256-bit byte-blends require AVX2 support!");
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// Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
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if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
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if (SDValue Masked =
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lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, DAG))
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return Masked;
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// Scale the blend by the number of bytes per element.
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@ -9488,8 +9489,8 @@ static SDValue lowerV4I32VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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Subtarget, DAG))
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return Blend;
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if (SDValue Masked =
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lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
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if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask,
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Zeroable, DAG))
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return Masked;
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// Use dedicated unpack instructions for masks that match their pattern.
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@ -10127,8 +10128,8 @@ static SDValue lowerV8I16VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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Subtarget, DAG))
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return Blend;
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if (SDValue Masked =
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lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
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if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask,
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Zeroable, DAG))
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return Masked;
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// Use dedicated unpack instructions for masks that match their pattern.
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@ -10366,8 +10367,8 @@ static SDValue lowerV16I8VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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return V;
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}
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if (SDValue Masked =
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lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
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if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask,
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Zeroable, DAG))
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return Masked;
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// Use dedicated unpack instructions for masks that match their pattern.
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@ -11881,7 +11882,8 @@ static SDValue lower256BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
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if (ElementBits < 32) {
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// No floating point type available, if we can't use the bit operations
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// for masking/blending then decompose into 128-bit vectors.
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if (SDValue V = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
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if (SDValue V =
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lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, DAG))
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return V;
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if (SDValue V = lowerVectorShuffleAsBitBlend(DL, VT, V1, V2, Mask, DAG))
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return V;
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