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AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit insts 

Summary:
The 32-bit instructions don't zero the high 16-bits like the 16-bit
instructions do.

Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D26828

llvm-svn: 287342
This commit is contained in:
Tom Stellard 2016-11-18 13:53:34 +00:00
parent 77382be56b
commit 01e65d2cfc
2 changed files with 64 additions and 3 deletions
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17
llvm/lib/Target/AMDGPU/VOP2Instructions.td
View File

@ -424,9 +424,20 @@ defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e32>;
defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e32>;
defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e32>;
defm : Arithmetic_i16_Pats<and, V_AND_B32_e32>;
defm : Arithmetic_i16_Pats<or, V_OR_B32_e32>;
defm : Arithmetic_i16_Pats<xor, V_XOR_B32_e32>;
def : Pat <
(and i16:$src0, i16:$src1),
(V_AND_B32_e32 $src0, $src1)
>;
def : Pat <
(or i16:$src0, i16:$src1),
(V_OR_B32_e32 $src0, $src1)
>;
def : Pat <
(xor i16:$src0, i16:$src1),
(V_XOR_B32_e32 $src0, $src1)
>;
defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;

50
llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll Normal file
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@ -0,0 +1,50 @@
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
; GCN-LABEL: and_zext:
; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
define void @and_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
%id = call i32 @llvm.amdgcn.workitem.id.x() #1
%ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
%a = load i16, i16 addrspace(1)* %in
%b = load i16, i16 addrspace(1)* %ptr
%c = add i16 %a, %b
%val16 = and i16 %c, %a
%val32 = zext i16 %val16 to i32
store i32 %val32, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: or_zext:
; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
define void @or_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
%id = call i32 @llvm.amdgcn.workitem.id.x() #1
%ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
%a = load i16, i16 addrspace(1)* %in
%b = load i16, i16 addrspace(1)* %ptr
%c = add i16 %a, %b
%val16 = or i16 %c, %a
%val32 = zext i16 %val16 to i32
store i32 %val32, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: xor_zext:
; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
define void @xor_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
%id = call i32 @llvm.amdgcn.workitem.id.x() #1
%ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
%a = load i16, i16 addrspace(1)* %in
%b = load i16, i16 addrspace(1)* %ptr
%c = add i16 %a, %b
%val16 = xor i16 %c, %a
%val32 = zext i16 %val16 to i32
store i32 %val32, i32 addrspace(1)* %out
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #1 = { nounwind readnone }