forked from OSchip/llvm-project
[RISCV] Cleanup a few section comments in RISCVInstrInfoVPseudos.td. NFC
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@ -2389,7 +2389,7 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions and patterns.
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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@ -2459,10 +2459,6 @@ foreach eew = EEWList in {
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defm PseudoVLE # eew # FF : VPseudoUSLoad;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// 12. Vector Integer Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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@ -2587,7 +2583,7 @@ defm PseudoVWMACCSU : VPseudoTernaryW_VV_VX;
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defm PseudoVWMACCUS : VPseudoTernaryW_VX</*IsFloat*/false>;
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//===----------------------------------------------------------------------===//
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// 12.15. Vector Integer Merge Instructions
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// 12.16. Vector Integer Merge Instructions
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//===----------------------------------------------------------------------===//
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defm PseudoVMERGE : VPseudoBinaryV_VM_XM_IM;
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@ -3222,7 +3218,7 @@ defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenabl
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defm "" : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>;
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//===----------------------------------------------------------------------===//
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// 12.15. Vector Integer Merge Instructions
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// 12.16. Vector Integer Merge Instructions
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//===----------------------------------------------------------------------===//
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defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
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