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Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names. 

llvm-svn: 155618
This commit is contained in:
Craig Topper 2012-04-26 06:40:15 +00:00
parent fc6a17b0a8
commit 08ccfbe57b
2 changed files with 9 additions and 13 deletions
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10
llvm/lib/Target/X86/X86.td
View File

@ -173,21 +173,19 @@ def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
// Sandy Bridge // Sandy Bridge
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
// rather than a superset. // rather than a superset.
// FIXME: Disabling AVX for now since it's not ready. def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
FeatureAES, FeatureCLMUL]>; FeatureAES, FeatureCLMUL]>;
// Ivy Bridge // Ivy Bridge
def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT, def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
FeatureAES, FeatureCLMUL, FeatureAES, FeatureCLMUL,
FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>; FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
// Haswell // Haswell
// FIXME: Disabling AVX/AVX2/FMA3 for now since it's not ready. def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,
def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
FeatureAES, FeatureCLMUL, FeatureRDRAND, FeatureAES, FeatureCLMUL, FeatureRDRAND,
FeatureF16C, FeatureFSGSBase, FeatureF16C, FeatureFSGSBase,
FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
FeatureBMI2]>; FeatureBMI2, FeatureFMA3]>;
def : Proc<"k6", [FeatureMMX]>; def : Proc<"k6", [FeatureMMX]>;
def : Proc<"k6-2", [Feature3DNow]>; def : Proc<"k6-2", [Feature3DNow]>;

12
llvm/lib/Target/X86/X86Subtarget.cpp
View File

@ -196,8 +196,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);} if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);} if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);} if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
// FIXME: AVX codegen support is not ready. if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }
//if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
@ -299,11 +298,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
HasBMI = true; HasBMI = true;
ToggleFeature(X86::FeatureBMI); ToggleFeature(X86::FeatureBMI);
} }
// FIXME: AVX2 codegen support is not ready. if ((EBX >> 5) & 0x1) {
//if ((EBX >> 5) & 0x1) { X86SSELevel = AVX2;
// X86SSELevel = AVX2; ToggleFeature(X86::FeatureAVX2);
// ToggleFeature(X86::FeatureAVX2); }
//}
if ((EBX >> 8) & 0x1) { if ((EBX >> 8) & 0x1) {
HasBMI2 = true; HasBMI2 = true;
ToggleFeature(X86::FeatureBMI2); ToggleFeature(X86::FeatureBMI2);