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Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps." 

This reverts commit r227488 as it was failing ARM bots.

llvm-svn: 227600
This commit is contained in:
Renato Golin 2015-01-30 19:18:58 +00:00
parent 5ce244889c
commit 0c9b51c16b
1 changed files with 7 additions and 7 deletions
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14
llvm/lib/Target/ARM/ARMFastISel.cpp
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@ -169,7 +169,7 @@ class ARMFastISel final : public FastISel {
bool isTypeLegal(Type *Ty, MVT &VT); bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT); bool isLoadTypeLegal(Type *Ty, MVT &VT);
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt, DebugLoc CurDL); bool isZExt);
bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment = 0, bool isZExt = true, unsigned Alignment = 0, bool isZExt = true,
bool allocReg = true); bool allocReg = true);
@ -1273,7 +1273,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
if (ARMPred == ARMCC::AL) return false; if (ARMPred == ARMCC::AL) return false;
// Emit the compare. // Emit the compare.
if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), CI->getDebugLoc())) if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
return false; return false;
unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
@ -1363,7 +1363,7 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
} }
bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt, DebugLoc CurDL) { bool isZExt) {
Type *Ty = Src1Value->getType(); Type *Ty = Src1Value->getType();
EVT SrcEVT = TLI.getValueType(Ty, true); EVT SrcEVT = TLI.getValueType(Ty, true);
if (!SrcEVT.isSimple()) return false; if (!SrcEVT.isSimple()) return false;
@ -1458,11 +1458,11 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
if (!UseImm) { if (!UseImm) {
SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, II) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
.addReg(SrcReg1).addReg(SrcReg2)); .addReg(SrcReg1).addReg(SrcReg2));
} else { } else {
MachineInstrBuilder MIB; MachineInstrBuilder MIB;
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, II) MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
.addReg(SrcReg1); .addReg(SrcReg1);
// Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
@ -1474,7 +1474,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
// For floating point we need to move the result to a comparison register // For floating point we need to move the result to a comparison register
// that we can then use for branches. // that we can then use for branches.
if (Ty->isFloatTy() || Ty->isDoubleTy()) if (Ty->isFloatTy() || Ty->isDoubleTy())
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM::FMSTAT))); TII.get(ARM::FMSTAT)));
return true; return true;
} }
@ -1489,7 +1489,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
if (ARMPred == ARMCC::AL) return false; if (ARMPred == ARMCC::AL) return false;
// Emit the compare. // Emit the compare.
if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), CI->getDebugLoc())) if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
return false; return false;
// Now set a register based on the comparison. Explicitly set the predicates // Now set a register based on the comparison. Explicitly set the predicates