forked from OSchip/llvm-project
Syntax hilight examples and add note about emacs/vim mode files
llvm-svn: 11146
This commit is contained in:
Chris Lattner
parent
149a2498d0
commit
1215e32eb7
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@ -38,11 +38,11 @@
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</ol>
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<li><a href="#backends">TableGen backends</a></li>
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<ol>
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<li><a href="#">x</a></li>
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<li><a href="#">todo</a></li>
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</ol>
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<li><a href="#codegenerator">The LLVM code generator</a></li>
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<ol>
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<li><a href="#">x</a></li>
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<li><a href="#">todo</a></li>
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</ol>
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</ul>
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@ -65,6 +65,12 @@ href="#backends">TableGen backend</a>" for processing. The current major user
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of TableGen is the <a href="#codegenerator">LLVM code generator</a>.
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</p>
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<p>
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Note that if you work on TableGen much, and use emacs or vim, that you can find
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an emacs "TableGen mode" and a vim language file in <tt>llvm/utils/emacs</tt>
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and <tt>llvm/utils/vim</tt> directory of your LLVM distribution, respectively.
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</p>
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</div>
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<!-- ======================================================================= -->
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@ -124,27 +130,27 @@ prints this (at the time of this writing):
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<p>
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<pre>
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...
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def ADDrr8 { // Instruction X86Inst I2A8 Pattern
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string Name = "add";
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string Namespace = "X86";
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list<Register> Uses = [];
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list<Register> Defs = [];
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bit isReturn = 0;
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bit isBranch = 0;
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bit isCall = 0;
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bit isTwoAddress = 1;
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bit isTerminator = 0;
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dag Pattern = (set R8, (plus R8, R8));
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bits<8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 0 };
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<b>def</b> ADDrr8 { <i>// Instruction X86Inst I2A8 Pattern</i>
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<b>string</b> Name = "add";
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<b>string</b> Namespace = "X86";
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<b>list</b><Register> Uses = [];
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<b>list</b><Register> Defs = [];
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<b>bit</b> isReturn = 0;
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<b>bit</b> isBranch = 0;
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<b>bit</b> isCall = 0;
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<b>bit</b> isTwoAddress = 1;
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<b>bit</b> isTerminator = 0;
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<b>dag</b> Pattern = (set R8, (plus R8, R8));
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<b>bits</b><8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 0 };
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Format Form = MRMDestReg;
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bits<5> FormBits = { 0, 0, 0, 1, 1 };
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<b>bits</b><5> FormBits = { 0, 0, 0, 1, 1 };
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ArgType Type = Arg8;
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bits<3> TypeBits = { 0, 0, 1 };
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bit hasOpSizePrefix = 0;
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bit printImplicitUses = 0;
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bits<4> Prefix = { 0, 0, 0, 0 };
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<b>bits</b><3> TypeBits = { 0, 0, 1 };
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<b>bit</b> hasOpSizePrefix = 0;
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<b>bit</b> printImplicitUses = 0;
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<b>bits</b><4> Prefix = { 0, 0, 0, 0 };
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FPFormat FPForm = ?;
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bits<3> FPFormBits = { 0, 0, 0 };
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<b>bits</b><3> FPFormBits = { 0, 0, 0 };
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}
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...
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</pre><p>
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@ -169,7 +175,7 @@ TableGen, all of the information was derived from the following definition:
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</p>
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<p><pre>
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def ADDrr8 : I2A8<"add", 0x00, MRMDestReg>,
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<b>def</b> ADDrr8 : I2A8<"add", 0x00, MRMDestReg>,
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Pattern<(set R8, (plus R8, R8))>;
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</pre></p>
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@ -284,32 +290,33 @@ TableGen types are:
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<p>
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<ul>
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<li>"<tt>bit</tt>" - A 'bit' is a boolean value that can hold either 0 or
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<li>"<tt><b>bit</b></tt>" - A 'bit' is a boolean value that can hold either 0 or
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1.</li>
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<li>"<tt>int</tt>" - The 'int' type represents a simple 32-bit integer value, such as 5.</li>
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<li>"<tt><b>int</b></tt>" - The 'int' type represents a simple 32-bit integer
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value, such as 5.</li>
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<li>"<tt>string</tt>" - The 'string' type represents an ordered sequence of
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characters of arbitrary length.</li>
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<li>"<tt><b>string</b></tt>" - The 'string' type represents an ordered sequence
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of characters of arbitrary length.</li>
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<li>"<tt>bits<n></tt>" - A 'bits' type is a arbitrary, but fixed, size
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integer that is broken up into individual bits. This type is useful because it
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can handle some bits being defined while others are undefined.</li>
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<li>"<tt><b>bits</b><n></tt>" - A 'bits' type is a arbitrary, but fixed,
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size integer that is broken up into individual bits. This type is useful
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because it can handle some bits being defined while others are undefined.</li>
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<li>"<tt>list<ty></tt>" - This type represents a list whose elements are
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some other type. The contained type is arbitrary: it can even be another list
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type.</li>
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<li>"<tt><b>list</b><ty></tt>" - This type represents a list whose
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elements are some other type. The contained type is arbitrary: it can even be
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another list type.</li>
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<li>Class type - Specifying a class name in a type context means that the
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defined value must be a subclass of the specified class. This is useful in
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conjunction with the "list" type, for example, to constrain the elements of the
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list to a common base class (e.g., a <tt>list<Register></tt> can only
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contain definitions derived from the "<tt>Register</tt>" class).</li>
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list to a common base class (e.g., a <tt><b>list</b><Register></tt> can
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only contain definitions derived from the "<tt>Register</tt>" class).</li>
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<li>"<tt>code</tt>" - This represents a big hunk of text. NOTE: I don't
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<li>"<tt><b>code</b></tt>" - This represents a big hunk of text. NOTE: I don't
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remember why this is distinct from string!</li>
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<li>"<tt>dag</tt>" - This type represents a nestable directed graph of
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<li>"<tt><b>dag</b></tt>" - This type represents a nestable directed graph of
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elements.</li>
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</ul>
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</p>
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@ -386,10 +393,10 @@ file:
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</p>
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<p><pre>
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class C { bit V = 1; }
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def X : C;
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def Y : C {
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string Greeting = "hello";
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<b>class</b> C { <b>bit</b> V = 1; }
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<b>def</b> X : C;
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<b>def</b> Y : C {
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<b>string</b> Greeting = "hello";
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}
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</pre></p>
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@ -431,8 +438,8 @@ value for example, a new class could be added to the example above, redefining
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the <tt>V</tt> field for all of its subclasses:</p>
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<p><pre>
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class D : C { let V = 0; }
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def Z : D;
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<b>class</b> D : C { let V = 0; }
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<b>def</b> Z : D;
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</pre></p>
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<p>
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@ -472,7 +479,7 @@ specified as a double quoted string immediately after the '<tt>include</tt>'
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keyword. Example:
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<p><pre>
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include "foo.td"
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<b>include</b> "foo.td"
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</pre></p>
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</div>
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@ -497,15 +504,15 @@ and one of more records to bind the values in. Here are some examples:
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</p>
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<p><pre>
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let isTerminator = 1, isReturn = 1 in
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def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
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<b>let</b> isTerminator = 1, isReturn = 1 <b>in</b>
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<b>def</b> RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>;
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
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def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
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def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
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<b>let</b> isCall = 1 <b>in</b>
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<i>// All calls clobber the non-callee saved registers...</i>
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<b>let</b> Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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<b>def</b> CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
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<b>def</b> CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
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<b>def</b> CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
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}
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</pre></p>
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