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Add XOP feature flag. 

llvm-svn: 145682
This commit is contained in:
Jan Sjödin 2011-12-02 15:14:37 +00:00
parent b67440367f
commit 1280eb1d06
3 changed files with 12 additions and 2 deletions
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7
llvm/lib/Target/X86/X86.td
View File

@ -91,6 +91,8 @@ def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
"Enable three-operand fused multiple-add">; "Enable three-operand fused multiple-add">;
def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
"Enable four-operand fused multiple-add">; "Enable four-operand fused multiple-add">;
def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
"Enable XOP instructions">;
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
"HasVectorUAMem", "true", "HasVectorUAMem", "true",
"Allow unaligned memory operands on vector/SIMD instructions">; "Allow unaligned memory operands on vector/SIMD instructions">;
@ -199,10 +201,11 @@ def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
// FIXME: Disabling AVX for now since it's not ready. // FIXME: Disabling AVX for now since it's not ready.
def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B, def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
FeatureAES, FeatureCLMUL, FeatureFMA4, FeatureAES, FeatureCLMUL, FeatureFMA4,
FeatureLZCNT]>; FeatureXOP, FeatureLZCNT]>;
def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B, def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
FeatureAES, FeatureCLMUL, FeatureFMA4, FeatureAES, FeatureCLMUL, FeatureFMA4,
FeatureF16C, FeatureLZCNT, FeatureBMI]>; FeatureXOP, FeatureF16C, FeatureLZCNT,
FeatureBMI]>;
def : Proc<"winchip-c6", [FeatureMMX]>; def : Proc<"winchip-c6", [FeatureMMX]>;
def : Proc<"winchip2", [Feature3DNow]>; def : Proc<"winchip2", [Feature3DNow]>;

3
llvm/lib/Target/X86/X86Subtarget.cpp
View File

@ -273,6 +273,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
if (IsAMD && ((ECX >> 16) & 0x1)) { if (IsAMD && ((ECX >> 16) & 0x1)) {
HasFMA4 = true; HasFMA4 = true;
ToggleFeature(X86::FeatureFMA4); ToggleFeature(X86::FeatureFMA4);
HasXOP = true;
ToggleFeature(X86::FeatureXOP);
} }
} }
} }
@ -317,6 +319,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
, HasCLMUL(false) , HasCLMUL(false)
, HasFMA3(false) , HasFMA3(false)
, HasFMA4(false) , HasFMA4(false)
, HasXOP(false)
, HasMOVBE(false) , HasMOVBE(false)
, HasRDRAND(false) , HasRDRAND(false)
, HasF16C(false) , HasF16C(false)

4
llvm/lib/Target/X86/X86Subtarget.h
View File

@ -93,6 +93,9 @@ protected:
/// HasFMA4 - Target has 4-operand fused multiply-add /// HasFMA4 - Target has 4-operand fused multiply-add
bool HasFMA4; bool HasFMA4;
/// HasXOP - Target has XOP instructions
bool HasXOP;
/// HasMOVBE - True if the processor has the MOVBE instruction. /// HasMOVBE - True if the processor has the MOVBE instruction.
bool HasMOVBE; bool HasMOVBE;
@ -198,6 +201,7 @@ public:
bool hasCLMUL() const { return HasCLMUL; } bool hasCLMUL() const { return HasCLMUL; }
bool hasFMA3() const { return HasFMA3; } bool hasFMA3() const { return HasFMA3; }
bool hasFMA4() const { return HasFMA4; } bool hasFMA4() const { return HasFMA4; }
bool hasXOP() const { return HasXOP; }
bool hasMOVBE() const { return HasMOVBE; } bool hasMOVBE() const { return HasMOVBE; }
bool hasRDRAND() const { return HasRDRAND; } bool hasRDRAND() const { return HasRDRAND; }
bool hasF16C() const { return HasF16C; } bool hasF16C() const { return HasF16C; }