forked from OSchip/llvm-project
ARM: disallow SP as Rn for Thumb2 TST & TEQ instructions
Using SP in this position is unpredictable in ARMv7. CMP and CMN are not affected, and of course v8 relaxes this requirement, but that's handled elsewhere. llvm-svn: 360242
This commit is contained in:
Tim Northover
parent
cced3ecc35
commit
18adcf331b
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@ -922,15 +922,15 @@ multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
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/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
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/// patterns. Similar to T2I_bin_irs except the instruction does not produce
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/// a explicit result, only implicitly set CPSR.
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multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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SDPatternOperator opnode> {
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let isCompare = 1, Defs = [CPSR] in {
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// shifted imm
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def ri : T2OneRegCmpImm<
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(outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
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(outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,
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opc, ".w\t$Rn, $imm",
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[(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
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[(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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@ -940,9 +940,9 @@ let isCompare = 1, Defs = [CPSR] in {
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}
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// register
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def rr : T2TwoRegCmp<
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(outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
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(outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,
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opc, ".w\t$Rn, $Rm",
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[(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
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[(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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@ -954,9 +954,9 @@ let isCompare = 1, Defs = [CPSR] in {
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}
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// shifted register
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def rs : T2OneRegCmpShiftedReg<
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(outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
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(outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
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opc, ".w\t$Rn, $ShiftedRm",
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[(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
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[(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>,
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Sched<[WriteCMPsi]> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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@ -970,9 +970,9 @@ let isCompare = 1, Defs = [CPSR] in {
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// No alias here for 'rr' version as not all instantiations of this
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// multiclass want one (CMP in particular, does not).
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def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
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(!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
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(!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>;
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def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
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(!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
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(!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>;
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}
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/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
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@ -3058,7 +3058,7 @@ def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
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//===----------------------------------------------------------------------===//
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// Comparison Instructions...
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//
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defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
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defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc,
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IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
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def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
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@ -3126,10 +3126,10 @@ def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
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def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
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(t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
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defm t2TST : T2I_cmp_irs<0b0000, "tst",
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defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
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BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
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defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
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defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR,
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IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
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BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
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@ -4551,9 +4551,9 @@ def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
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def : t2InstAlias<"cmn${p} $Rn, $Rm",
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(t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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def : t2InstAlias<"teq${p} $Rn, $Rm",
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(t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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(t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
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def : t2InstAlias<"tst${p} $Rn, $Rm",
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(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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(t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
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// Memory barriers
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def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
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@ -21,7 +21,7 @@ body: |
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%0(s32) = COPY $r0
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; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
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%1(s1) = G_TRUNC %0(s32)
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; CHECK: [[COND:%[0-9]+]]:gprnopc = COPY [[COND32]]
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; CHECK: [[COND:%[0-9]+]]:rgpr = COPY [[COND32]]
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G_BRCOND %1(s1), %bb.1
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; CHECK: t2TSTri [[COND]], 1, 14, $noreg, implicit-def $cpsr
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@ -26,10 +26,9 @@ body: |
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; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
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%2(s1) = G_TRUNC %1(s32)
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; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGY]]
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%3(s32) = G_SELECT %2(s1), %0, %1
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; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
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; CHECK: t2TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr
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; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
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$r0 = COPY %3(s32)
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@ -65,7 +64,7 @@ body: |
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; CHECK: [[VREGC32:%[0-9]+]]:gpr = COPY $r2
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%3(s1) = G_TRUNC %2(s32)
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; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGC32]]
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; CHECK: [[VREGC:%[0-9]+]]:rgpr = COPY [[VREGC32]]
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%4(p0) = G_SELECT %3(s1), %0, %1
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; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
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@ -151,3 +151,17 @@ foo2:
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adds r0
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@ CHECK-ERRORS: error: too few operands for instruction
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@ CHECK-ERRORS: error: too few operands for instruction
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tst sp, #3
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tst sp, r5
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tst sp, r5, lsl #3
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@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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teq sp, #5
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teq sp, r7
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teq sp, r9, lsl #2
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@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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