forked from OSchip/llvm-project
[SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
This also removes a pattern from RISCV that is no longer needed since the sexti32 on the LHS of the srem in the pattern implies the result is sign extended so the sign_extend_inreg should be removed in DAG combine now. Reviewed By: luismarques, RKSimon Differential Revision: https://reviews.llvm.org/D97133
This commit is contained in:
Craig Topper
parent
bae04a3e2d
commit
1a6c1ac686
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@ -3869,6 +3869,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
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(VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
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return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
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}
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case ISD::SREM:
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// The sign bit is the LHS's sign bit, except when the result of the
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// remainder is zero. The magnitude of the result should be less than or
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// equal to the magnitude of the LHS. Therefore, the result should have
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// at least as many sign bits as the left hand side.
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return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
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case ISD::TRUNCATE: {
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// Check if the sign bits of source go down as far as the truncated value.
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unsigned NumSrcBits = Op.getOperand(0).getScalarValueSizeInBits();
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@ -93,7 +93,4 @@ def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
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// produce a result where res[63:32]=0 and res[31]=1.
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def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
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(REMW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
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(sexti32 GPR:$rs2)), i32),
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(REMW GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtM, IsRV64]
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@ -1,29 +1,29 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
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; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
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; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
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; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
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; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
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@ -70,67 +70,43 @@ entry:
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}
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define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
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; GP32R0R2-LABEL: srem_i8:
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; GP32R0R2: # %bb.0: # %entry
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; GP32R0R2-NEXT: div $zero, $4, $5
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; GP32R0R2-NEXT: teq $5, $zero, 7
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; GP32R0R2-NEXT: mfhi $1
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; GP32R0R2-NEXT: sll $1, $1, 24
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; GP32R0R2-NEXT: jr $ra
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; GP32R0R2-NEXT: sra $2, $1, 24
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;
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; GP32R2R5-LABEL: srem_i8:
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; GP32R2R5: # %bb.0: # %entry
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; GP32R2R5-NEXT: div $zero, $4, $5
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; GP32R2R5-NEXT: teq $5, $zero, 7
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; GP32R2R5-NEXT: mfhi $1
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; GP32R2R5-NEXT: jr $ra
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; GP32R2R5-NEXT: seb $2, $1
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; GP32-LABEL: srem_i8:
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; GP32: # %bb.0: # %entry
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; GP32-NEXT: div $zero, $4, $5
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; GP32-NEXT: teq $5, $zero, 7
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; GP32-NEXT: jr $ra
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; GP32-NEXT: mfhi $2
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;
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; GP32R6-LABEL: srem_i8:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: mod $1, $4, $5
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; GP32R6-NEXT: mod $2, $4, $5
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; GP32R6-NEXT: teq $5, $zero, 7
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; GP32R6-NEXT: jr $ra
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; GP32R6-NEXT: seb $2, $1
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; GP32R6-NEXT: jrc $ra
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;
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; GP64R0R1-LABEL: srem_i8:
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; GP64R0R1: # %bb.0: # %entry
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; GP64R0R1-NEXT: div $zero, $4, $5
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; GP64R0R1-NEXT: teq $5, $zero, 7
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; GP64R0R1-NEXT: mfhi $1
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; GP64R0R1-NEXT: sll $1, $1, 24
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; GP64R0R1-NEXT: jr $ra
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; GP64R0R1-NEXT: sra $2, $1, 24
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;
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; GP64R2R5-LABEL: srem_i8:
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; GP64R2R5: # %bb.0: # %entry
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; GP64R2R5-NEXT: div $zero, $4, $5
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; GP64R2R5-NEXT: teq $5, $zero, 7
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; GP64R2R5-NEXT: mfhi $1
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; GP64R2R5-NEXT: jr $ra
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; GP64R2R5-NEXT: seb $2, $1
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; GP64-LABEL: srem_i8:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: div $zero, $4, $5
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; GP64-NEXT: teq $5, $zero, 7
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; GP64-NEXT: jr $ra
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; GP64-NEXT: mfhi $2
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;
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; GP64R6-LABEL: srem_i8:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: mod $1, $4, $5
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; GP64R6-NEXT: mod $2, $4, $5
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; GP64R6-NEXT: teq $5, $zero, 7
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; GP64R6-NEXT: jr $ra
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; GP64R6-NEXT: seb $2, $1
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; GP64R6-NEXT: jrc $ra
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;
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; MMR3-LABEL: srem_i8:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: div $zero, $4, $5
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; MMR3-NEXT: teq $5, $zero, 7
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; MMR3-NEXT: mfhi16 $1
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; MMR3-NEXT: jr $ra
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; MMR3-NEXT: seb $2, $1
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; MMR3-NEXT: mfhi16 $2
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; MMR3-NEXT: jrc $ra
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;
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; MMR6-LABEL: srem_i8:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: mod $1, $4, $5
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; MMR6-NEXT: mod $2, $4, $5
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; MMR6-NEXT: teq $5, $zero, 7
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; MMR6-NEXT: seb $2, $1
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; MMR6-NEXT: jrc $ra
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entry:
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%r = srem i8 %a, %b
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@ -138,67 +114,43 @@ entry:
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}
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define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
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; GP32R0R2-LABEL: srem_i16:
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; GP32R0R2: # %bb.0: # %entry
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; GP32R0R2-NEXT: div $zero, $4, $5
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; GP32R0R2-NEXT: teq $5, $zero, 7
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; GP32R0R2-NEXT: mfhi $1
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; GP32R0R2-NEXT: sll $1, $1, 16
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; GP32R0R2-NEXT: jr $ra
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; GP32R0R2-NEXT: sra $2, $1, 16
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;
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; GP32R2R5-LABEL: srem_i16:
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; GP32R2R5: # %bb.0: # %entry
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; GP32R2R5-NEXT: div $zero, $4, $5
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; GP32R2R5-NEXT: teq $5, $zero, 7
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; GP32R2R5-NEXT: mfhi $1
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; GP32R2R5-NEXT: jr $ra
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; GP32R2R5-NEXT: seh $2, $1
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; GP32-LABEL: srem_i16:
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; GP32: # %bb.0: # %entry
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; GP32-NEXT: div $zero, $4, $5
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; GP32-NEXT: teq $5, $zero, 7
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; GP32-NEXT: jr $ra
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; GP32-NEXT: mfhi $2
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;
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; GP32R6-LABEL: srem_i16:
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; GP32R6: # %bb.0: # %entry
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; GP32R6-NEXT: mod $1, $4, $5
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; GP32R6-NEXT: mod $2, $4, $5
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; GP32R6-NEXT: teq $5, $zero, 7
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; GP32R6-NEXT: jr $ra
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; GP32R6-NEXT: seh $2, $1
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; GP32R6-NEXT: jrc $ra
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;
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; GP64R0R1-LABEL: srem_i16:
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; GP64R0R1: # %bb.0: # %entry
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; GP64R0R1-NEXT: div $zero, $4, $5
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; GP64R0R1-NEXT: teq $5, $zero, 7
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; GP64R0R1-NEXT: mfhi $1
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; GP64R0R1-NEXT: sll $1, $1, 16
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; GP64R0R1-NEXT: jr $ra
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; GP64R0R1-NEXT: sra $2, $1, 16
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;
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; GP64R2R5-LABEL: srem_i16:
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; GP64R2R5: # %bb.0: # %entry
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; GP64R2R5-NEXT: div $zero, $4, $5
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; GP64R2R5-NEXT: teq $5, $zero, 7
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; GP64R2R5-NEXT: mfhi $1
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; GP64R2R5-NEXT: jr $ra
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; GP64R2R5-NEXT: seh $2, $1
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; GP64-LABEL: srem_i16:
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; GP64: # %bb.0: # %entry
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; GP64-NEXT: div $zero, $4, $5
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; GP64-NEXT: teq $5, $zero, 7
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; GP64-NEXT: jr $ra
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; GP64-NEXT: mfhi $2
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;
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; GP64R6-LABEL: srem_i16:
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; GP64R6: # %bb.0: # %entry
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; GP64R6-NEXT: mod $1, $4, $5
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; GP64R6-NEXT: mod $2, $4, $5
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; GP64R6-NEXT: teq $5, $zero, 7
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; GP64R6-NEXT: jr $ra
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; GP64R6-NEXT: seh $2, $1
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; GP64R6-NEXT: jrc $ra
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;
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; MMR3-LABEL: srem_i16:
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; MMR3: # %bb.0: # %entry
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; MMR3-NEXT: div $zero, $4, $5
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; MMR3-NEXT: teq $5, $zero, 7
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; MMR3-NEXT: mfhi16 $1
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; MMR3-NEXT: jr $ra
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; MMR3-NEXT: seh $2, $1
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; MMR3-NEXT: mfhi16 $2
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; MMR3-NEXT: jrc $ra
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;
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; MMR6-LABEL: srem_i16:
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; MMR6: # %bb.0: # %entry
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; MMR6-NEXT: mod $1, $4, $5
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; MMR6-NEXT: mod $2, $4, $5
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; MMR6-NEXT: teq $5, $zero, 7
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; MMR6-NEXT: seh $2, $1
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; MMR6-NEXT: jrc $ra
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entry:
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%r = srem i16 %a, %b
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@ -1092,8 +1092,6 @@ define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind
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; RV64IM-LABEL: sext_remw_sext_sext_i8:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: remw a0, a0, a1
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; RV64IM-NEXT: slli a0, a0, 56
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; RV64IM-NEXT: srai a0, a0, 56
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; RV64IM-NEXT: ret
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%1 = srem i8 %a, %b
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ret i8 %1
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@ -1103,8 +1101,6 @@ define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b) noun
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; RV64IM-LABEL: sext_remw_sext_sext_i16:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: remw a0, a0, a1
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; RV64IM-NEXT: slli a0, a0, 48
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; RV64IM-NEXT: srai a0, a0, 48
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; RV64IM-NEXT: ret
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%1 = srem i16 %a, %b
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ret i16 %1
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@ -1127,7 +1123,6 @@ define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b)
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; RV64IM-LABEL: sext_i32_remw_sext_zext_i16:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: ret
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%1 = sext i16 %a to i32
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%2 = zext i16 %b to i32
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