forked from OSchip/llvm-project
[x86] simplify code in combineExtractSubvector; NFC
Only the 1st fold is attempted pre-legalization, but it requires legal (simple) types too, so we don't need an EVT in any of the code. llvm-svn: 354674
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@ -41960,7 +41960,10 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG,
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// Capture the original wide type in the likely case that we need to bitcast
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// back to this type.
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EVT VT = N->getValueType(0);
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if (!N->getValueType(0).isSimple())
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return SDValue();
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MVT VT = N->getSimpleValueType(0);
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EVT WideVecVT = N->getOperand(0).getValueType();
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SDValue WideVec = peekThroughBitcasts(N->getOperand(0));
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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@ -41986,64 +41989,63 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG,
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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MVT OpVT = N->getSimpleValueType(0);
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SDValue InVec = N->getOperand(0);
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unsigned IdxVal = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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if (ISD::isBuildVectorAllZeros(InVec.getNode()))
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return getZeroVector(OpVT, Subtarget, DAG, SDLoc(N));
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return getZeroVector(VT, Subtarget, DAG, SDLoc(N));
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if (ISD::isBuildVectorAllOnes(InVec.getNode())) {
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if (OpVT.getScalarType() == MVT::i1)
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return DAG.getConstant(1, SDLoc(N), OpVT);
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return getOnesVector(OpVT, DAG, SDLoc(N));
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if (VT.getScalarType() == MVT::i1)
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return DAG.getConstant(1, SDLoc(N), VT);
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return getOnesVector(VT, DAG, SDLoc(N));
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}
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if (InVec.getOpcode() == ISD::BUILD_VECTOR)
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return DAG.getBuildVector(
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OpVT, SDLoc(N),
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InVec.getNode()->ops().slice(IdxVal, OpVT.getVectorNumElements()));
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VT, SDLoc(N),
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InVec.getNode()->ops().slice(IdxVal, VT.getVectorNumElements()));
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// If we're extracting the lowest subvector and we're the only user,
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// we may be able to perform this with a smaller vector width.
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if (IdxVal == 0 && InVec.hasOneUse()) {
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unsigned InOpcode = InVec.getOpcode();
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if (OpVT == MVT::v2f64 && InVec.getValueType() == MVT::v4f64) {
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if (VT == MVT::v2f64 && InVec.getValueType() == MVT::v4f64) {
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// v2f64 CVTDQ2PD(v4i32).
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if (InOpcode == ISD::SINT_TO_FP &&
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InVec.getOperand(0).getValueType() == MVT::v4i32) {
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return DAG.getNode(X86ISD::CVTSI2P, SDLoc(N), OpVT, InVec.getOperand(0));
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return DAG.getNode(X86ISD::CVTSI2P, SDLoc(N), VT, InVec.getOperand(0));
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}
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// v2f64 CVTPS2PD(v4f32).
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if (InOpcode == ISD::FP_EXTEND &&
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InVec.getOperand(0).getValueType() == MVT::v4f32) {
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return DAG.getNode(X86ISD::VFPEXT, SDLoc(N), OpVT, InVec.getOperand(0));
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return DAG.getNode(X86ISD::VFPEXT, SDLoc(N), VT, InVec.getOperand(0));
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}
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}
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if ((InOpcode == ISD::ZERO_EXTEND || InOpcode == ISD::SIGN_EXTEND) &&
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OpVT.is128BitVector() &&
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VT.is128BitVector() &&
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InVec.getOperand(0).getSimpleValueType().is128BitVector()) {
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unsigned ExtOp =
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InOpcode == ISD::ZERO_EXTEND ? ISD::ZERO_EXTEND_VECTOR_INREG
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: ISD::SIGN_EXTEND_VECTOR_INREG;
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return DAG.getNode(ExtOp, SDLoc(N), OpVT, InVec.getOperand(0));
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InOpcode == ISD::ZERO_EXTEND ? ISD::ZERO_EXTEND_VECTOR_INREG
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: ISD::SIGN_EXTEND_VECTOR_INREG;
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return DAG.getNode(ExtOp, SDLoc(N), VT, InVec.getOperand(0));
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}
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if ((InOpcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
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InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) &&
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OpVT.is128BitVector() &&
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VT.is128BitVector() &&
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InVec.getOperand(0).getSimpleValueType().is128BitVector()) {
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return DAG.getNode(InOpcode, SDLoc(N), OpVT, InVec.getOperand(0));
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return DAG.getNode(InOpcode, SDLoc(N), VT, InVec.getOperand(0));
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}
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if (InOpcode == ISD::BITCAST) {
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// TODO - do this for target shuffles in general.
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SDValue InVecBC = peekThroughOneUseBitcasts(InVec);
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if (InVecBC.getOpcode() == X86ISD::PSHUFB && OpVT.is128BitVector()) {
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if (InVecBC.getOpcode() == X86ISD::PSHUFB && VT.is128BitVector()) {
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SDLoc DL(N);
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SDValue SubPSHUFB =
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DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
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extract128BitVector(InVecBC.getOperand(0), 0, DAG, DL),
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extract128BitVector(InVecBC.getOperand(1), 0, DAG, DL));
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return DAG.getBitcast(OpVT, SubPSHUFB);
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return DAG.getBitcast(VT, SubPSHUFB);
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}
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}
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}
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