wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[X86] Const correct some helper functions X86InstrInfo.cpp. NFC 

llvm-svn: 349440
This commit is contained in:
Craig Topper 2018-12-18 04:58:05 +00:00
parent f549812599
commit 1ff7356f96
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -718,7 +718,7 @@ bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
} }
/// Check whether the shift count for a machine operand is non-zero. /// Check whether the shift count for a machine operand is non-zero.
inline static unsigned getTruncatedShiftCount(MachineInstr &MI, inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
unsigned ShiftAmtOperandIdx) { unsigned ShiftAmtOperandIdx) {
// The shift count is six bits with the REX.W prefix and five bits without. // The shift count is six bits with the REX.W prefix and five bits without.
unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31; unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
@ -3421,9 +3421,10 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
/// This function can be extended later on. /// This function can be extended later on.
/// SrcReg, SrcRegs: register operands for FlagI. /// SrcReg, SrcRegs: register operands for FlagI.
/// ImmValue: immediate for FlagI if it takes an immediate. /// ImmValue: immediate for FlagI if it takes an immediate.
inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg, inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
unsigned SrcReg2, int ImmMask, unsigned SrcReg, unsigned SrcReg2,
int ImmValue, MachineInstr &OI) { int ImmMask, int ImmValue,
const MachineInstr &OI) {
if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) || if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
(FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) || (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
(FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) || (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
@ -3454,7 +3455,7 @@ inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
/// Check whether the definition can be converted /// Check whether the definition can be converted
/// to remove a comparison against zero. /// to remove a comparison against zero.
inline static bool isDefConvertible(MachineInstr &MI) { inline static bool isDefConvertible(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: return false; default: return false;
@ -3563,7 +3564,7 @@ inline static bool isDefConvertible(MachineInstr &MI) {
} }
/// Check whether the use can be converted to remove a comparison against zero. /// Check whether the use can be converted to remove a comparison against zero.
static X86::CondCode isUseDefConvertible(MachineInstr &MI) { static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: return X86::COND_INVALID; default: return X86::COND_INVALID;
case X86::LZCNT16rr: case X86::LZCNT16rm: case X86::LZCNT16rr: case X86::LZCNT16rm: