forked from OSchip/llvm-project
[X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. llvm-svn: 329414
This commit is contained in:
parent
61f704e4bd
commit
22d25a08ae
|
@ -2119,13 +2119,13 @@ def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst),
|
|||
|
||||
// Flag instructions
|
||||
let SchedRW = [WriteALU] in {
|
||||
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
|
||||
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
|
||||
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>;
|
||||
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>;
|
||||
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
|
||||
def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
|
||||
def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
|
||||
def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
|
||||
def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
|
||||
def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;
|
||||
|
||||
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
|
||||
}
|
||||
|
|
|
@ -641,12 +641,10 @@ def IIC_CMPXCHG_8B : InstrItinClass;
|
|||
def IIC_CMPXCHG_16B : InstrItinClass;
|
||||
def IIC_LODS : InstrItinClass;
|
||||
def IIC_OUTS : InstrItinClass;
|
||||
def IIC_CLC : InstrItinClass;
|
||||
def IIC_CLC_CMC_STC : InstrItinClass;
|
||||
def IIC_CLD : InstrItinClass;
|
||||
def IIC_CLI : InstrItinClass;
|
||||
def IIC_CMC : InstrItinClass;
|
||||
def IIC_CLTS : InstrItinClass;
|
||||
def IIC_STC : InstrItinClass;
|
||||
def IIC_STI : InstrItinClass;
|
||||
def IIC_STD : InstrItinClass;
|
||||
def IIC_XLAT : InstrItinClass;
|
||||
|
|
|
@ -523,12 +523,10 @@ def AtomItineraries : ProcessorItineraries<
|
|||
InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CLC_CMC_STC, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
|
||||
|
|
Loading…
Reference in New Issue