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[NFC][Test][PowerPC] Add one test to verify the behavior of vector 

mul/add for v8i16
This commit is contained in:
QingShan Zhang 2020-03-25 02:37:26 +00:00
parent baa78179fe
commit 2488ea428d
1 changed files with 26 additions and 0 deletions
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26
llvm/test/CodeGen/PowerPC/vmladduhm.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8
define <8 x i16> @mul(<8 x i16> %m, <8 x i16> %n) {
; CHECK-LABEL: mul:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor 36, 36, 36
; CHECK-NEXT: vmladduhm 2, 2, 3, 4
; CHECK-NEXT: blr
entry:
%0 = mul <8 x i16> %m, %n
ret <8 x i16> %0
}
define <8 x i16> @madd(<8 x i16> %m, <8 x i16> %n, <8 x i16> %o) {
; CHECK-LABEL: madd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxlxor 37, 37, 37
; CHECK-NEXT: vmladduhm 2, 2, 3, 5
; CHECK-NEXT: vadduhm 2, 2, 4
; CHECK-NEXT: blr
entry:
%0 = mul <8 x i16> %m, %n
%1 = add <8 x i16> %0, %o
ret <8 x i16> %1
}