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CodeGen: Correct specification of PHI nodes 

They do have a def machine operand.

Fixing the definition is necessary for an upcoming patch.

Differential Revision: http://reviews.llvm.org/D18384

llvm-svn: 264607
This commit is contained in:
Matthias Braun 2016-03-28 18:18:41 +00:00
parent 6a6bc750d5
commit 2bd8eeb6b7
2 changed files with 3 additions and 3 deletions
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2
llvm/include/llvm/Target/Target.td
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@ -773,7 +773,7 @@ class InstrInfo {
let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
Namespace = "TargetOpcode" in {
def PHI : Instruction {
let OutOperandList = (outs);
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
}

4
llvm/test/CodeGen/AMDGPU/valu-i1.ll
View File

@ -138,11 +138,11 @@ exit:
; SI: BB#4:
; SI: buffer_store_dword
; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
; SI: BB3_5:
; SI: s_or_b64 exec, exec, [[ORNEG2]]
; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
; SI: s_cbranch_execnz BB3_3