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[PowerPC] Implement missing ISA 2.06 instructions. 

Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement
them and add corresponding test cases in this patch.

llvm-svn: 291116
This commit is contained in:
Tony Jiang 2017-01-05 15:00:45 +00:00
parent e27b058de3
commit 3a2f00b024
6 changed files with 62 additions and 7 deletions
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2
llvm/lib/Target/PowerPC/PPCISelLowering.h
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@ -47,7 +47,7 @@ namespace llvm {
FCTIDZ, FCTIWZ,
/// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
/// unsigned integers.
/// unsigned integers with round toward zero.
FCTIDUZ, FCTIWUZ,
/// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in

3
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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@ -1154,6 +1154,9 @@ defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
"fctid", "$frD, $frB", IIC_FPGeneral,
[]>, isPPC64;
defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB),
"fctidu", "$frD, $frB", IIC_FPGeneral,
[]>, isPPC64;
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
"fctidz", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;

6
llvm/lib/Target/PowerPC/PPCInstrFormats.td
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@ -603,6 +603,12 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = 0;
}
class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
let FRA = 0;
}
// Used for QPX
class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>

8
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -2172,11 +2172,19 @@ let isCompare = 1, hasSideEffects = 0 in {
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
}
def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"ftdiv $crD, $fA, $fB", IIC_FPCompare>;
def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
"ftsqrt $crD, $fB", IIC_FPCompare>;
let Uses = [RM] in {
let hasSideEffects = 0 in {
defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiw", "$frD, $frB", IIC_FPGeneral,
[]>;
defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiwu", "$frD, $frB", IIC_FPGeneral,
[]>;
defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiwz", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfctiwz f64:$frB))]>;

18
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
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@ -231,6 +231,12 @@
# CHECK: fctid. 2, 3
0xfc 0x40 0x1e 0x5d
# CHECK: fctidu 2, 3
0xfc 0x40 0x1f 0x5c
# CHECK: fctidu. 2, 3
0xfc 0x40 0x1f 0x5d
# CHECK: fctidz 2, 3
0xfc 0x40 0x1e 0x5e
@ -249,6 +255,12 @@
# CHECK: fctiw. 2, 3
0xfc 0x40 0x18 0x1d
# CHECK: fctiwu 2, 3
0xfc 0x40 0x19 0x1c
# CHECK: fctiwu. 2, 3
0xfc 0x40 0x19 0x1d
# CHECK: fctiwz 2, 3
0xfc 0x40 0x18 0x1e
@ -309,6 +321,12 @@
# CHECK: frim. 2, 3
0xfc 0x40 0x1b 0xd1
# CHECK: ftdiv 2, 3, 4
0xfd 0x03 0x21 0x00
#CHECK: ftsqrt 2, 3
0xfd,0x00,0x19,0x40
# CHECK: fcmpu 2, 3, 4
0xfd 0x03 0x20 0x00

32
llvm/test/MC/PowerPC/ppc64-encoding-fp.s
View File

@ -188,8 +188,14 @@
# CHECK-BE: frsqrtes. 2, 3 # encoding: [0xec,0x40,0x18,0x35]
# CHECK-LE: frsqrtes. 2, 3 # encoding: [0x35,0x18,0x40,0xec]
frsqrtes. 2, 3
# FIXME: ftdiv 2, 3, 4
# FIXME: ftsqrt 2, 3, 4
# CHECK-BE: ftdiv 2, 3, 4 # encoding: [0xfd,0x03,0x21,0x00]
# CHECK-LE: ftdiv 2, 3, 4 # encoding: [0x00,0x21,0x03,0xfd]
ftdiv 2, 3, 4
# CHECK-BE: ftsqrt 2, 3 # encoding: [0xfd,0x00,0x19,0x40]
# CHECK-LE: ftsqrt 2, 3 # encoding: [0x40,0x19,0x00,0xfd]
ftsqrt 2, 3
# CHECK-BE: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a]
# CHECK-LE: fmadd 2, 3, 4, 5 # encoding: [0x3a,0x29,0x43,0xfc]
@ -255,34 +261,48 @@
# CHECK-BE: fctid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5d]
# CHECK-LE: fctid. 2, 3 # encoding: [0x5d,0x1e,0x40,0xfc]
fctid. 2, 3
# CHECK-BE: fctidu 2, 3 # encoding: [0xfc,0x40,0x1f,0x5c]
# CHECK-LE: fctidu 2, 3 # encoding: [0x5c,0x1f,0x40,0xfc]
fctidu 2, 3
# CHECK-BE: fctidu. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5d]
# CHECK-LE: fctidu. 2, 3 # encoding: [0x5d,0x1f,0x40,0xfc]
fctidu. 2, 3
# CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e]
# CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc]
fctidz 2, 3
# CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f]
# CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc]
fctidz. 2, 3
# FIXME: fctidu 2, 3
# FIXME: fctidu. 2, 3
# CHECK-BE: fctiduz 2, 3 # encoding: [0xfc,0x40,0x1f,0x5e]
# CHECK-LE: fctiduz 2, 3 # encoding: [0x5e,0x1f,0x40,0xfc]
fctiduz 2, 3
# CHECK-BE: fctiduz. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5f]
# CHECK-LE: fctiduz. 2, 3 # encoding: [0x5f,0x1f,0x40,0xfc]
fctiduz. 2, 3
# CHECK-BE: fctiw 2, 3 # encoding: [0xfc,0x40,0x18,0x1c]
# CHECK-LE: fctiw 2, 3 # encoding: [0x1c,0x18,0x40,0xfc]
fctiw 2, 3
# CHECK-BE: fctiw. 2, 3 # encoding: [0xfc,0x40,0x18,0x1d]
# CHECK-LE: fctiw. 2, 3 # encoding: [0x1d,0x18,0x40,0xfc]
fctiw. 2, 3
# CHECK-BE: fctiwu 2, 3 # encoding: [0xfc,0x40,0x19,0x1c]
# CHECK-LE: fctiwu 2, 3 # encoding: [0x1c,0x19,0x40,0xfc]
fctiwu 2, 3
# CHECK-BE: fctiwu. 2, 3 # encoding: [0xfc,0x40,0x19,0x1d]
# CHECK-LE: fctiwu. 2, 3 # encoding: [0x1d,0x19,0x40,0xfc]
fctiwu. 2, 3
# CHECK-BE: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e]
# CHECK-LE: fctiwz 2, 3 # encoding: [0x1e,0x18,0x40,0xfc]
fctiwz 2, 3
# CHECK-BE: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f]
# CHECK-LE: fctiwz. 2, 3 # encoding: [0x1f,0x18,0x40,0xfc]
fctiwz. 2, 3
# FIXME: fctiwu 2, 3
# FIXME: fctiwu. 2, 3
# CHECK-BE: fctiwuz 2, 3 # encoding: [0xfc,0x40,0x19,0x1e]
# CHECK-LE: fctiwuz 2, 3 # encoding: [0x1e,0x19,0x40,0xfc]
fctiwuz 2, 3