forked from OSchip/llvm-project
				
			[X86] Add test for rotate combining when add X, X is used instead of shl X, 1. NFC
llvm-svn: 370203
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			@ -280,3 +280,17 @@ define <2 x i64> @no_extract_udiv(<2 x i64> %i) nounwind {
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  %out = or <2 x i64> %lhs_shift, %rhs_div
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  ret <2 x i64> %out
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}
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; DAGCombiner transforms shl X, 1 into add X, X.
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define <4 x i32> @extract_add_1(<4 x i32> %i) nounwind {
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; CHECK-LABEL: extract_add_1:
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; CHECK:       # %bb.0:
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; CHECK-NEXT:    vpaddd %xmm0, %xmm0, %xmm1
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; CHECK-NEXT:    vpsrld $31, %xmm0, %xmm0
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; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
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; CHECK-NEXT:    ret{{[l|q]}}
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  %ii = add <4 x i32> %i, %i
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  %rhs = lshr <4 x i32> %i, <i32 31, i32 31, i32 31, i32 31>
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  %out = or <4 x i32> %ii, %rhs
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  ret <4 x i32> %out
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}
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			@ -265,3 +265,26 @@ define i8 @no_extract_udiv(i8 %i) nounwind {
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  %out = or i8 %lhs_shift, %rhs_div
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  ret i8 %out
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}
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; DAGCombiner transforms shl X, 1 into add X, X.
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define i32 @extract_add_1(i32 %i) nounwind {
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; X86-LABEL: extract_add_1:
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; X86:       # %bb.0:
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; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT:    leal (%ecx,%ecx), %eax
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; X86-NEXT:    shrl $31, %ecx
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; X86-NEXT:    orl %ecx, %eax
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; X86-NEXT:    retl
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;
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; X64-LABEL: extract_add_1:
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; X64:       # %bb.0:
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; X64-NEXT:    # kill: def $edi killed $edi def $rdi
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; X64-NEXT:    leal (%rdi,%rdi), %eax
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; X64-NEXT:    shrl $31, %edi
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; X64-NEXT:    orl %edi, %eax
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; X64-NEXT:    retq
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  %ii = add i32 %i, %i
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  %rhs = lshr i32 %i, 31
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  %out = or i32 %ii, %rhs
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  ret i32 %out
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}
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