forked from OSchip/llvm-project
[RISCV] Correct types in tablegen multiclasses found by D95874.
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@ -52,7 +52,7 @@ def SDTRVVVecReduce : SDTypeProfile<1, 2, [
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foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR"] in
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def rvv_vecreduce_#kind : SDNode<"RISCVISD::VECREDUCE_"#kind, SDTRVVVecReduce>;
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multiclass VPatUSLoadStoreSDNode<LLVMType type,
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multiclass VPatUSLoadStoreSDNode<ValueType type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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