forked from OSchip/llvm-project
[GISel]: Add combine for G_FABS to G_FABS
https://reviews.llvm.org/D87554 Patch adds one new GICombinerRule for G_FABS. The combine rule folds G_FABS(G_FABS(X)) to G_FABS(X). Patch additionally adds new combiner tests for the AArch64 target to test this new combiner rule. Patch by mkitzan.
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@ -280,6 +280,10 @@ public:
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/// Transform fneg(fneg(x)) to x.
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bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg);
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/// Match fabs(fabs(x)) to fabs(x).
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bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
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bool applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
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/// Return true if any explicit use operand on \p MI is defined by a
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/// G_IMPLICIT_DEF.
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bool matchAnyExplicitUseIsUndef(MachineInstr &MI);
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@ -403,6 +403,15 @@ def unmerge_merge : GICombineRule<
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(apply [{ return Helper.applyCombineUnmergeMergeToPlainValues(*${d}, ${info}); }])
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>;
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// Fold (fabs (fabs x)) -> (fabs x).
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def fabs_fabs_fold_matchinfo : GIDefMatchData<"Register">;
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def fabs_fabs_fold: GICombineRule<
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(defs root:$root, fabs_fabs_fold_matchinfo:$matchinfo),
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(match (wip_match_opcode G_FABS):$root,
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[{ return Helper.matchCombineFAbsOfFAbs(*${root}, ${matchinfo}); }]),
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(apply [{ return Helper.applyCombineFAbsOfFAbs(*${root}, ${matchinfo}); }])
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>;
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// FIXME: These should use the custom predicate feature once it lands.
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def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
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undef_to_negative_one,
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@ -433,4 +442,5 @@ def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
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shl_ashr_to_sext_inreg, sext_inreg_of_load,
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width_reduction_combines, select_combines,
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known_bits_simplifications, ext_ext_fold,
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not_cmp_fold, opt_brcond_by_inverting_cond, unmerge_merge]>;
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not_cmp_fold, opt_brcond_by_inverting_cond,
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unmerge_merge, fabs_fabs_fold]>;
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@ -1878,6 +1878,21 @@ bool CombinerHelper::matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg) {
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return mi_match(SrcReg, MRI, m_GFNeg(m_Reg(Reg)));
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}
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bool CombinerHelper::matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src) {
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assert(MI.getOpcode() == TargetOpcode::G_FABS && "Expected a G_FABS");
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Src = MI.getOperand(1).getReg();
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Register AbsSrc;
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return mi_match(Src, MRI, m_GFabs(m_Reg(AbsSrc)));
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}
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bool CombinerHelper::applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src) {
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assert(MI.getOpcode() == TargetOpcode::G_FABS && "Expected a G_FABS");
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Register Dst = MI.getOperand(0).getReg();
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MI.eraseFromParent();
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replaceRegWith(MRI, Dst, Src);
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return true;
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}
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bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) {
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return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
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return MO.isReg() &&
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@ -0,0 +1,32 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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---
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name: test_combine_fabs_fabs
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: test_combine_fabs_fabs
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
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; CHECK: $w0 = COPY [[FABS]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = G_FABS %0(s32)
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%2:_(s32) = G_FABS %1(s32)
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$w0 = COPY %2(s32)
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...
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---
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name: test_combine_fabs_fabs_vec
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: test_combine_fabs_fabs_vec
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $x0
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; CHECK: [[FABS:%[0-9]+]]:_(<2 x s32>) = G_FABS [[COPY]]
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; CHECK: $x0 = COPY [[FABS]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $x0
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%1:_(<2 x s32>) = G_FABS %0(<2 x s32>)
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%2:_(<2 x s32>) = G_FABS %1(<2 x s32>)
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$x0 = COPY %2(<2 x s32>)
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...
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