forked from OSchip/llvm-project
[InstCombine][NFCI] Add test coverage to onehot_merge.ll
Prep work for upcoming patch D64275. llvm-svn: 365729
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Huihui Zhang
parent
9066e5f832
commit
51f5079191
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@ -187,3 +187,148 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c
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%or = and i1 %t2, %t4
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ret i1 %or
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}
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; Shift-of-signbit replaced with 'icmp s*' for both sides
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 %c1, i32 %c2) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%t0 = shl i32 %k, %c1
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%t1 = icmp sgt i32 %t0, -1
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%t2 = shl i32 %k, %c2
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%t3 = icmp sgt i32 %t2, -1
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%or = or i1 %t1, %t3
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ret i1 %or
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}
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define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 %c1, i32 %c2) {
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; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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%t0 = shl i32 %k, %c1
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%t1 = icmp slt i32 %t0, 0
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%t2 = shl i32 %k, %c2
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%t3 = icmp slt i32 %t2, 0
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%or = and i1 %t1, %t3
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ret i1 %or
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}
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; Extra use
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; Expect to fold
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(i32 %k, i32 %c1, i32 %c2, i32* %p) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]]
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; CHECK-NEXT: store i32 [[T0]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%t0 = shl i32 1, %c1
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store i32 %t0, i32* %p ; extra use of shl
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%t1 = and i32 %t0, %k
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%t2 = icmp eq i32 %t1, 0
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%t3 = shl i32 %k, %c2
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%t4 = icmp sgt i32 %t3, -1
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%or = or i1 %t2, %t4
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ret i1 %or
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}
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; Not fold
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(i32 %k, i32 %c1, i32 %c2, i32* %p) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]
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; CHECK-NEXT: store i32 [[T1]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%t0 = shl i32 1, %c1
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%t1 = and i32 %t0, %k
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store i32 %t1, i32* %p ; extra use of and
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%t2 = icmp eq i32 %t1, 0
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%t3 = shl i32 %k, %c2
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%t4 = icmp sgt i32 %t3, -1
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%or = or i1 %t2, %t4
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ret i1 %or
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}
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; Not fold
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(i32 %k, i32 %c1, i32 %c2, i1* %p) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: store i1 [[T2]], i1* [[P:%.*]], align 1
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%t0 = shl i32 1, %c1
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%t1 = and i32 %t0, %k
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%t2 = icmp eq i32 %t1, 0
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store i1 %t2, i1* %p ; extra use of cmp
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%t3 = shl i32 %k, %c2
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%t4 = icmp sgt i32 %t3, -1
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%or = or i1 %t2, %t4
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ret i1 %or
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}
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; Not fold
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, i32* %p) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: store i32 [[T3]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%t0 = shl i32 1, %c1
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%t1 = and i32 %t0, %k
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%t2 = icmp eq i32 %t1, 0
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%t3 = shl i32 %k, %c2
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store i32 %t3, i32* %p ; extra use of shl
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%t4 = icmp sgt i32 %t3, -1
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%or = or i1 %t2, %t4
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ret i1 %or
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}
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; Not fold
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define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, i1* %p) {
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; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]
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; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1
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; CHECK-NEXT: store i1 [[T4]], i1* [[P:%.*]], align 1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%t0 = shl i32 1, %c1
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%t1 = and i32 %t0, %k
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%t2 = icmp eq i32 %t1, 0
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%t3 = shl i32 %k, %c2
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%t4 = icmp sgt i32 %t3, -1
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store i1 %t4, i1* %p ; extra use of cmp
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%or = or i1 %t2, %t4
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ret i1 %or
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}
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