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Fix for PR29010 

This is a fix for https://llvm.org/bugs/show_bug.cgi?id=29010
Root cause of the bug is that the register class of the machine instruction operand does not fully reflect if this registers that can be allocated.
Both for i386 and x86_64 the operand's register class is VR128RegClass and thus contains xmm0-xmm15, though in i386 we can only use xmm0-xmm8.
In order to get the actual allocable registers of the class we need to use RegisterClassInfo.

Differential Revision: https://reviews.llvm.org/D23613

llvm-svn: 278954
This commit is contained in:
Marina Yatsina 2016-08-17 19:07:40 +00:00
parent 6ad7dfcc1e
commit 53ce3f9d02
2 changed files with 17 additions and 1 deletions
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6
llvm/lib/CodeGen/ExecutionDepsFix.cpp
View File

@ -26,6 +26,7 @@
#include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/Support/Allocator.h" #include "llvm/Support/Allocator.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
@ -137,6 +138,7 @@ class ExeDepsFix : public MachineFunctionPass {
MachineFunction *MF; MachineFunction *MF;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
RegisterClassInfo RegClassInfo;
std::vector<SmallVector<int, 1>> AliasMap; std::vector<SmallVector<int, 1>> AliasMap;
const unsigned NumRegs; const unsigned NumRegs;
LiveReg *LiveRegs; LiveReg *LiveRegs;
@ -509,7 +511,8 @@ void ExeDepsFix::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
// max clearance or clearance higher than Pref. // max clearance or clearance higher than Pref.
unsigned MaxClearance = 0; unsigned MaxClearance = 0;
unsigned MaxClearanceReg = OriginalReg; unsigned MaxClearanceReg = OriginalReg;
for (auto Reg : OpRC->getRegisters()) { ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
for (auto Reg : Order) {
assert(AliasMap[Reg].size() == 1 && assert(AliasMap[Reg].size() == 1 &&
"Reg is expected to be mapped to a single index"); "Reg is expected to be mapped to a single index");
int RCrx = *regIndices(Reg).begin(); int RCrx = *regIndices(Reg).begin();
@ -785,6 +788,7 @@ bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
MF = &mf; MF = &mf;
TII = MF->getSubtarget().getInstrInfo(); TII = MF->getSubtarget().getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo(); TRI = MF->getSubtarget().getRegisterInfo();
RegClassInfo.runOnMachineFunction(mf);
LiveRegs = nullptr; LiveRegs = nullptr;
assert(NumRegs == RC->getNumRegs() && "Bad regclass"); assert(NumRegs == RC->getNumRegs() && "Bad regclass");

12
llvm/test/CodeGen/X86/pr29010.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s
; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM
define float @only_xmm0_7(i32 %arg) {
top:
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"()
%tmp1 = sitofp i32 %arg to float
ret float %tmp1
;CHECK-LABEL:@only_xmm0_7
;CHECK: vcvtsi2ssl {{.*}}, {{%xmm[0-7]+}}, {{%xmm[0-7]+}}
}