wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AMDGPU/GlobalISel: Implement applyMappingImpl less incorrectly 

We're checking the current register bank of the registers in the
instruction, but the mapping may have inserted cross bank copies and
is expecting to replace the registers.

We mostly get away with this currently, because VGPR->SGPR copies are
illegal, and we assume this won't happen. In a future change, we'll
start relying on more cross register bank copies being inserted, and
this starts to break down.
This commit is contained in:
Matt Arsenault 2019-12-23 14:39:01 -05:00 committed by Matt Arsenault
parent 4c6c4e2fce
commit 5eed4e2664
1 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -1069,11 +1069,11 @@ bool AMDGPURegisterBankInfo::applyMappingWideLoad(MachineInstr &MI,
// If the pointer is an SGPR, we have nothing to do. // If the pointer is an SGPR, we have nothing to do.
if (SrcRegs.empty()) { if (SrcRegs.empty()) {
Register PtrReg = MI.getOperand(1).getReg(); const RegisterBank *PtrBank =
const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
if (PtrBank == &AMDGPU::SGPRRegBank) if (PtrBank == &AMDGPU::SGPRRegBank)
return false; return false;
SrcRegs.push_back(PtrReg); SrcRegs.push_back(MI.getOperand(1).getReg());
} }
assert(LoadSize % MaxNonSmrdLoadSize == 0); assert(LoadSize % MaxNonSmrdLoadSize == 0);
@ -1458,7 +1458,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
if (DstTy != LLT::scalar(16)) if (DstTy != LLT::scalar(16))
break; break;
const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI); const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::VGPRRegBank) if (DstBank == &AMDGPU::VGPRRegBank)
break; break;
@ -1479,7 +1480,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
case AMDGPU::G_UMIN: case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX: { case AMDGPU::G_UMAX: {
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI); const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::VGPRRegBank) if (DstBank == &AMDGPU::VGPRRegBank)
break; break;
@ -1516,7 +1518,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
bool Signed = Opc == AMDGPU::G_SEXT; bool Signed = Opc == AMDGPU::G_SEXT;
MachineIRBuilder B(MI); MachineIRBuilder B(MI);
const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI); const RegisterBank *SrcBank =
OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
@ -1618,7 +1621,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
substituteSimpleCopyRegs(OpdMapper, 1); substituteSimpleCopyRegs(OpdMapper, 1);
substituteSimpleCopyRegs(OpdMapper, 2); substituteSimpleCopyRegs(OpdMapper, 2);
const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI); const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::SGPRRegBank) if (DstBank == &AMDGPU::SGPRRegBank)
break; // Can use S_PACK_* instructions. break; // Can use S_PACK_* instructions.
@ -1628,8 +1632,10 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
Register Hi = MI.getOperand(2).getReg(); Register Hi = MI.getOperand(2).getReg();
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
const RegisterBank *BankLo = getRegBank(Lo, MRI, *TRI); const RegisterBank *BankLo =
const RegisterBank *BankHi = getRegBank(Hi, MRI, *TRI); OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
const RegisterBank *BankHi =
OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
Register ZextLo; Register ZextLo;
Register ShiftHi; Register ShiftHi;
@ -1710,7 +1716,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
= OpdMapper.getInstrMapping().getOperandMapping(0); = OpdMapper.getInstrMapping().getOperandMapping(0);
// FIXME: Should be getting from mapping or not? // FIXME: Should be getting from mapping or not?
const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI); const RegisterBank *SrcBank =
OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
MRI.setRegBank(DstReg, *DstMapping.BreakDown[0].RegBank); MRI.setRegBank(DstReg, *DstMapping.BreakDown[0].RegBank);
MRI.setRegBank(CastSrc.getReg(0), *SrcBank); MRI.setRegBank(CastSrc.getReg(0), *SrcBank);
MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank); MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank);
@ -1775,9 +1782,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
auto InsHi = B.buildInsertVectorElement(Vec32, InsLo, InsRegs[1], IdxHi); auto InsHi = B.buildInsertVectorElement(Vec32, InsLo, InsRegs[1], IdxHi);
B.buildBitcast(DstReg, InsHi); B.buildBitcast(DstReg, InsHi);
const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI); const RegisterBank *DstBank =
const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI); OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
const RegisterBank *InsSrcBank = getRegBank(InsReg, MRI, *TRI); const RegisterBank *SrcBank =
OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
const RegisterBank *InsSrcBank =
OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
MRI.setRegBank(InsReg, *InsSrcBank); MRI.setRegBank(InsReg, *InsSrcBank);
MRI.setRegBank(CastSrc.getReg(0), *SrcBank); MRI.setRegBank(CastSrc.getReg(0), *SrcBank);