forked from OSchip/llvm-project
parent
37709c3584
commit
654cb0a761
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@ -77,13 +77,26 @@ def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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let Uses = [SR] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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} // isCommutable
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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@ -93,24 +106,44 @@ def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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(implicit SR)]>;
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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}
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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let Uses = [SR] in {
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def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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}
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// FIXME: Provide proper encoding!
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