forked from OSchip/llvm-project
parent
abb6d6d618
commit
6f2067659d
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@ -475,10 +475,8 @@ def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> {
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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GPRClass::iterator I;
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if (Subtarget.isThumb1Only()) {
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I = THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
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return I;
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}
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
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if (Subtarget.isTargetDarwin()) {
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if (Subtarget.isR9Reserved())
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