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Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 

llvm-svn: 128965
This commit is contained in:
Owen Anderson 2011-04-05 23:55:28 +00:00
parent 086f7080d6
commit 867846b1f0
2 changed files with 42 additions and 65 deletions
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22
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5029,7 +5029,12 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case ARM::ADCSSrs: case ARM::ADCSSrs:
case ARM::SBCSSri: case ARM::SBCSSri:
case ARM::SBCSSrr: case ARM::SBCSSrr:
case ARM::SBCSSrs: { case ARM::SBCSSrs:
case ARM::RSBSri:
case ARM::RSBSrr:
case ARM::RSBSrs:
case ARM::RSCSri:
case ARM::RSCSrs: {
unsigned OldOpc = MI->getOpcode(); unsigned OldOpc = MI->getOpcode();
unsigned Opc = 0; unsigned Opc = 0;
switch (OldOpc) { switch (OldOpc) {
@ -5051,6 +5056,21 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case ARM::SBCSSrs: case ARM::SBCSSrs:
Opc = ARM::SBCrs; Opc = ARM::SBCrs;
break; break;
case ARM::RSBSri:
Opc = ARM::RSBri;
break;
case ARM::RSBSrr:
Opc = ARM::RSBrr;
break;
case ARM::RSBSrs:
Opc = ARM::RSBrs;
break;
case ARM::RSCSri:
Opc = ARM::RSCri;
break;
case ARM::RSCSrs:
Opc = ARM::RSCrs;
break;
default: default:
llvm_unreachable("Unknown opcode?"); llvm_unreachable("Unknown opcode?");
} }

85
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -935,7 +935,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
} }
} }
// Carry setting variants // Carry setting variants
let isCodeGenOnly = 1, Defs = [CPSR] in { // NOTE: CPSR def omitted because it will be handled by the custom inserter.
let usesCustomInserter = 1 in {
multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> { multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
Size4Bytes, IIC_iALUi, Size4Bytes, IIC_iALUi,
@ -2243,44 +2244,17 @@ def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
} }
// RSB with 's' bit set. // RSB with 's' bit set.
let isCodeGenOnly = 1, Defs = [CPSR] in { // NOTE: CPSR def omitted because it will be handled by the custom inserter.
def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, let usesCustomInserter = 1 in {
IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm", def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
[(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> { Size4Bytes, IIC_iALUi,
bits<4> Rd; [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
bits<4> Rn; def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
bits<12> imm; Size4Bytes, IIC_iALUr,
let Inst{25} = 1; [/* For disassembly only; pattern left blank */]>;
let Inst{20} = 1; def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
let Inst{15-12} = Rd; Size4Bytes, IIC_iALUsr,
let Inst{19-16} = Rn; [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
let Inst{11-0} = imm;
}
def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
} }
let Uses = [CPSR] in { let Uses = [CPSR] in {
@ -2325,33 +2299,16 @@ def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
} }
// FIXME: Allow these to be predicated. // FIXME: Allow these to be predicated.
let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in { // NOTE: CPSR def omitted because it will be handled by the custom inserter.
def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), let usesCustomInserter = 1, Uses = [CPSR] in {
DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm", def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
Size4Bytes, IIC_iALUi,
[(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
Requires<[IsARM]> { Requires<[IsARM]>;
bits<4> Rd; def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
bits<4> Rn; Size4Bytes, IIC_iALUsr,
bits<12> imm;
let Inst{25} = 1;
let Inst{20} = 1;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
}
def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>, [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
Requires<[IsARM]> { Requires<[IsARM]>;
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{11-0} = shift;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
} }
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.