forked from OSchip/llvm-project
[Hexagon] Create HexagonISelDAGToDAG.h, NFC
llvm-svn: 317904
This commit is contained in:
Krzysztof Parzyszek
parent
b8c68c67dc
commit
89765acc6c
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@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "Hexagon.h"
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#include "HexagonISelDAGToDAG.h"
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#include "HexagonISelLowering.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonTargetMachine.h"
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@ -50,116 +51,9 @@ static cl::opt<bool> CheckSingleUse("hexagon-isel-su", cl::Hidden,
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// Instruction Selector Implementation
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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#define GET_DAGISEL_BODY HexagonDAGToDAGISel
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/// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class HexagonDAGToDAGISel : public SelectionDAGISel {
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const HexagonSubtarget *HST;
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const HexagonInstrInfo *HII;
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const HexagonRegisterInfo *HRI;
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public:
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explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
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HRI(nullptr) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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// Reset the subtarget each time through.
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HST = &MF.getSubtarget<HexagonSubtarget>();
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HII = HST->getInstrInfo();
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HRI = HST->getRegisterInfo();
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SelectionDAGISel::runOnMachineFunction(MF);
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return true;
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}
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bool ComplexPatternFuncMutatesDAG() const override {
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return true;
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}
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void PreprocessISelDAG() override;
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void EmitFunctionEntryCode() override;
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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inline bool SelectAddrGA(SDValue &N, SDValue &R);
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inline bool SelectAddrGP(SDValue &N, SDValue &R);
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inline bool SelectAnyImm(SDValue &N, SDValue &R);
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inline bool SelectAnyInt(SDValue &N, SDValue &R);
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bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
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bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
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uint32_t LogAlign);
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bool SelectAddrFI(SDValue &N, SDValue &R);
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bool DetectUseSxtw(SDValue &N, SDValue &R);
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inline bool SelectAnyImm0(SDValue &N, SDValue &R);
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inline bool SelectAnyImm1(SDValue &N, SDValue &R);
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inline bool SelectAnyImm2(SDValue &N, SDValue &R);
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inline bool SelectAnyImm3(SDValue &N, SDValue &R);
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StringRef getPassName() const override {
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return "Hexagon DAG->DAG Pattern Instruction Selection";
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}
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// Generate a machine instruction node corresponding to the circ/brev
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// load intrinsic.
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MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
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// Given the circ/brev load intrinsic and the already generated machine
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// instruction, generate the appropriate store (that is a part of the
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// intrinsic's functionality).
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SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
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void SelectFrameIndex(SDNode *N);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
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void SelectLoad(SDNode *N);
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void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
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void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
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void SelectStore(SDNode *N);
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void SelectSHL(SDNode *N);
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void SelectZeroExtend(SDNode *N);
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void SelectIntrinsicWChain(SDNode *N);
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void SelectIntrinsicWOChain(SDNode *N);
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void SelectConstant(SDNode *N);
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void SelectConstantFP(SDNode *N);
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void SelectBitcast(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "HexagonGenDAGISel.inc"
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#include "HexagonGenDAGISel.inc"
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private:
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bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
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bool isOrEquivalentToAdd(const SDNode *N) const;
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bool isAlignedMemNode(const MemSDNode *N) const;
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bool isSmallStackStore(const StoreSDNode *N) const;
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bool isPositiveHalfWord(const SDNode *N) const;
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bool hasOneUse(const SDNode *N) const;
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// DAG preprocessing functions.
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void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
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void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
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void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
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void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
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SmallDenseMap<SDNode *,int> RootWeights;
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SmallDenseMap<SDNode *,int> RootHeights;
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SmallDenseMap<const Value *,int> GAUsesInFunction;
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int getWeight(SDNode *N);
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int getHeight(SDNode *N);
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SDValue getMultiplierForSHL(SDNode *N);
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SDValue factorOutPowerOf2(SDValue V, unsigned Power);
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unsigned getUsesInFunction(const Value *V);
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SDValue balanceSubTree(SDNode *N, bool Factorize = false);
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void rebalanceAddressTrees();
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}; // end HexagonDAGToDAGISel
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} // end anonymous namespace
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/// createHexagonISelDag - This pass converts a legalized DAG into a
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/// createHexagonISelDag - This pass converts a legalized DAG into a
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/// Hexagon-specific DAG, ready for instruction scheduling.
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/// Hexagon-specific DAG, ready for instruction scheduling.
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///
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///
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@ -0,0 +1,136 @@
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//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Hexagon specific code to select Hexagon machine instructions for
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// SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/CodeGen.h"
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#include <vector>
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namespace llvm {
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class MachineFunction;
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class HexagonDAGToDAGISel : public SelectionDAGISel {
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const HexagonSubtarget *HST;
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const HexagonInstrInfo *HII;
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const HexagonRegisterInfo *HRI;
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public:
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explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
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HRI(nullptr) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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// Reset the subtarget each time through.
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HST = &MF.getSubtarget<HexagonSubtarget>();
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HII = HST->getInstrInfo();
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HRI = HST->getRegisterInfo();
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SelectionDAGISel::runOnMachineFunction(MF);
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return true;
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}
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bool ComplexPatternFuncMutatesDAG() const override {
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return true;
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}
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void PreprocessISelDAG() override;
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void EmitFunctionEntryCode() override;
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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inline bool SelectAddrGA(SDValue &N, SDValue &R);
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inline bool SelectAddrGP(SDValue &N, SDValue &R);
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inline bool SelectAnyImm(SDValue &N, SDValue &R);
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inline bool SelectAnyInt(SDValue &N, SDValue &R);
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bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
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bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
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uint32_t LogAlign);
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bool SelectAddrFI(SDValue &N, SDValue &R);
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bool DetectUseSxtw(SDValue &N, SDValue &R);
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inline bool SelectAnyImm0(SDValue &N, SDValue &R);
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inline bool SelectAnyImm1(SDValue &N, SDValue &R);
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inline bool SelectAnyImm2(SDValue &N, SDValue &R);
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inline bool SelectAnyImm3(SDValue &N, SDValue &R);
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StringRef getPassName() const override {
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return "Hexagon DAG->DAG Pattern Instruction Selection";
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}
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// Generate a machine instruction node corresponding to the circ/brev
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// load intrinsic.
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MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
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// Given the circ/brev load intrinsic and the already generated machine
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// instruction, generate the appropriate store (that is a part of the
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// intrinsic's functionality).
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SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
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void SelectFrameIndex(SDNode *N);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
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void SelectLoad(SDNode *N);
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void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
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void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
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void SelectStore(SDNode *N);
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void SelectSHL(SDNode *N);
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void SelectZeroExtend(SDNode *N);
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void SelectIntrinsicWChain(SDNode *N);
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void SelectIntrinsicWOChain(SDNode *N);
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void SelectConstant(SDNode *N);
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void SelectConstantFP(SDNode *N);
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void SelectBitcast(SDNode *N);
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void SelectVectorShuffle(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#define GET_DAGISEL_DECL
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#include "HexagonGenDAGISel.inc"
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private:
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bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
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bool isOrEquivalentToAdd(const SDNode *N) const;
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bool isAlignedMemNode(const MemSDNode *N) const;
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bool isSmallStackStore(const StoreSDNode *N) const;
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bool isPositiveHalfWord(const SDNode *N) const;
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bool hasOneUse(const SDNode *N) const;
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// DAG preprocessing functions.
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void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
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void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
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void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
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void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
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SmallDenseMap<SDNode *,int> RootWeights;
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SmallDenseMap<SDNode *,int> RootHeights;
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SmallDenseMap<const Value *,int> GAUsesInFunction;
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int getWeight(SDNode *N);
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int getHeight(SDNode *N);
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SDValue getMultiplierForSHL(SDNode *N);
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SDValue factorOutPowerOf2(SDValue V, unsigned Power);
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unsigned getUsesInFunction(const Value *V);
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SDValue balanceSubTree(SDNode *N, bool Factorize = false);
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void rebalanceAddressTrees();
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}; // end HexagonDAGToDAGISel
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}
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
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