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Redefine mfhi/lo and mthi/lo instructions. 

llvm-svn: 142214
This commit is contained in:
Akira Hatanaka 2011-10-17 18:24:15 +00:00
parent 38ff264857
commit 8c446be204
2 changed files with 16 additions and 35 deletions
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26
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -57,19 +57,6 @@ class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
// Move from Hi/Lo
let shamt = 0 in {
let rs = 0, rt = 0 in
class MoveFromLOHI64<bits<6> func, string instr_asm>:
FR<0x00, func, (outs CPU64Regs:$dst), (ins),
!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
let rt = 0, rd = 0 in
class MoveToLOHI64<bits<6> func, string instr_asm>:
FR<0x00, func, (outs), (ins CPU64Regs:$src),
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
}
// Count Leading Ones/Zeros in Word
class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
@ -157,15 +144,10 @@ def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
let Defs = [HI64] in
def MTHI64 : MoveToLOHI64<0x11, "mthi">;
let Defs = [LO64] in
def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
let Uses = [HI64] in
def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
let Uses = [LO64] in
def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
/// Count Leading
def DCLZ : CountLeading64<0x24, "dclz",

25
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -488,20 +488,24 @@ class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
// Move from Hi/Lo
class MoveFromLOHI<bits<6> func, string instr_asm>:
FR<0x00, func, (outs CPURegs:$rd), (ins),
class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
list<Register> UseRegs>:
FR<0x00, func, (outs RC:$rd), (ins),
!strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
let rs = 0;
let rt = 0;
let shamt = 0;
let Uses = UseRegs;
}
class MoveToLOHI<bits<6> func, string instr_asm>:
FR<0x00, func, (outs), (ins CPURegs:$rs),
class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs),
!strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
let rt = 0;
let rd = 0;
let shamt = 0;
let Defs = DefRegs;
}
class EffectiveAddress<string instr_asm> :
@ -739,15 +743,10 @@ def MULTu : Mult32<0x19, "multu", IIImul>;
def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
let Defs = [HI] in
def MTHI : MoveToLOHI<0x11, "mthi">;
let Defs = [LO] in
def MTLO : MoveToLOHI<0x13, "mtlo">;
let Uses = [HI] in
def MFHI : MoveFromLOHI<0x10, "mfhi">;
let Uses = [LO] in
def MFLO : MoveFromLOHI<0x12, "mflo">;
def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
/// Sign Ext In Register Instructions.
def SEB : SignExtInReg<0x10, "seb", i8>;